Some FPGA FIR resources :
https://www.fpga4student.com/2016/11/image-processing-on-fpga-verilog.html
https://www.dspguide.com/ch6/3.htm
https://www.hackster.io/whitney-knitter/dsp-for-fpga-simple-fir-filter-in-verilog-91208d
https://github.com/samiyaalizaidi/FIR-Filter
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Here’s the FIR filter output using samiya alizaidi’s code lightly modified (to take in only 2 bits and output 3 bits) :
Next step is to be able to turn it on and off with a button to see the effect better, and to have a potentiometer (or even a new board with a bunch of bots) to vary the taps live somehow.
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I want to convolute in place an image recorded in BRAM. This will be a combination of down sampling and convoluting in parallel.