Author: marrs

Finished NO SCHOOL ! Here are some things I learned regarding the board itself :

• the low profile VGA connector is a nightmare, never again.
• the reset button needs to go elsewhere as Lattice IceCube doesn’t like pin 66 for some reason
• the 3D printed cases suck, not necessary and doesn’t have NO SCHOOL on it
• the pads for the bias trim knob kept breaking, not sure if it is bad PCB manufacturing or poor design. Also a bit too hard for beginners to solder this part.
• the portable low power soldering irons sucked for this
• I can remove the caps and 1K resistors for the button debouncing
• the video pass through mode is annoying to set up (needing an audio cable, remembering which pin is H and V sync etc.)
• People like the mechanical keys
• The VCC and GND is useful for powering a breadboard with other video mods

Regarding the hands on video glitching workshop :

• Breadboards and pinout of the VGA connector tough to get the hang of.
• Important to make a safe space – you can’t hurt yourself, nothing valuable here, etc.
• I did a free-style open-ended workshop but still ended up starting with asking the participants to :
  • use jumpers to plug in their board to a VGA cable (though I should have skipped this and went directly to plugging in to the breadboard)
  • use jumpers to plug in their board to a breadboard and then to the VGA cable
  • use switches to turn on or off different channels
  • use pots to attenuate different color channels
  • use coil of wire to make a delay
  • use LM386 to amplify
  • 74*04 to invert
  • Circuit bending the schmitt trigger
  • Mixing signals: 74*86 to XOR, or just pots
• I should have gotten them to put audio in the pass through mode !
• Forgot to ask them to make BLACK AND WHITE from color
• There was no oscilloscope or function generator to work with, I should have brought a logic analyzer too
• Karl Marx was a big hit
• I hand drew some schematics (pinouts of various chips, circuits etc.) and printed them, then would project and draw on the big board the pinouts
• They have difficulty with the translation of schematic to actual connections.
• I can imagine a board made specifically for this workshop which would have an FPGA or Arduino (but without any buttons just as a kind of screen saver) and would connect to a breadboard, breaking out the different pins, where you could do things. This would have gotten around the pain of plugging in jumpers to the VGA connectors, and would be far less work than making the entire FPGA béchamel board. It could be a super basic atmega with just a knob to select patterns.

****

Paul suggests adding to my open source FPGA video synth page :

• A nicer README that explains the project in depth and uses Markdown to make things easier and nicer to read and navigate
• An explanation of how people can use and contribute to the project
• A better organization of the files in the project
• Selecting a licence
• Using git on the PC instead of Github

I really like the idea of doing a super page with gifs explaining what codes do, compiled binaries and commented verilog codes.

I wonder if I could work on a series of separate effects, each with it’s own module, that would allow people to add effects.

Looking in to open source hardware projects for inspiration:

• OPEN MV (https://github.com/openmv/openmv): Uses an 32-bit Arm Cortex-M4 chip with DSPs.
• MUTABLE INSTRUMENTS (https://pichenettes.github.io/mutable-instruments-documentation/) Open source versions of classic eurorack modules

I have rebuilt the git repo and it looks way better now :

What I’ve learned :

• I can import Eagle boards (but not my schematics so far) into KiCAD but I should build using KiCAD from now on for open source projects
• I can take all the energy I was using to make this website and put it into making an awesome README for my project
• A project can almost start with the README, so that it is clear from the beginning what the thing is and what it does

I’ve also promised to send boards to people, perhaps a little prematurely ! Ideally it would be easy for people to upgrade their firmware, this way I could freeze the hardware design and just focus on making code. But this would require giving them a programmer ?

******

Check out this FPGA graphics tutorial : https://projectf.io/posts/fpga-graphics/

Essentially, start by generating a pixel clock for the chosen resolution. Look up standard VGA timings and set up the parameters for blanking etc. Set up a counter and a display enable signal, and then create shapes by using equality operators and colors.

This racing the beam tutorial (https://tomverbeure.github.io/rtl/2018/11/26/Racing-the-Beam-Ray-Tracer.html) explains that if you don’t have enough space for a frame buffer you can have a line buffer, or even a pixel buffer, if you can compute things fast enough. Later in the series using raster font in a simple way, sprites in ROM and scaling them, and creating a simple color LUT.

The screen buffer article is informative : https://projectf.io/posts/framebuffers/ . Especially how to scale up 160×120 framebuffer up to 640×480. Also this one on the three different strategies for making FPGA animations : https://projectf.io/posts/animated-shapes/

This looks like a good FPGA tutorial resource I wasn’t aware of:

• http://asic-world.com/verilog/index.html
• https://projectf.io/tutorials/
• http://fpgacpu.ca/fpga/index.html
• https://zipcpu.com/tutorial/
• http://www.doe.carleton.ca/~gallan/478/pdfs/PeterVrlR.pdf
• https://fpgaer.tech/?p=191

To decode HDMI found this : https://warmcat.com/hardware%20design/hdmi/fpga/2015/10/22/hdmi-capture-and-analysis-fpga-project-3.html

**********

I think this project has been a victim of a certain amount of magical thinking. The machine will only do what it can do and what it is asked to do. Yes, it’s possible to glitch the machine but ultimately there are no surprises unless you don’t fully understand what you’re asking the machine to do. It’s all deterministic. Learning the history of graphics is super cool but you are just reproducing old techniques, there isn’t going to be some hidden type of graphic expression that was missed by everyone that you are going to unlock somehow. It’s just colors on a screen in the end…

It’s ultimately an activity I enjoy, and it is best to share things you enjoy with other people. I should connect with other people making things !

*****

Here’s the final pcf :

// CLOCK

set_io clk_in 49

// HDMI OUT

set_io hdmi_p[0] 139 -io_std SB_LVCMOS
set_io hdmi_p[2] 78 -io_std SB_LVCMOS
set_io hdmi_p[1] 80 -io_std SB_LVCMOS
set_io hdmi_p[3] 137 -io_std SB_LVCMOS

set_io hdmi_n[0] 138 -io_std SB_LVCMOS
set_io hdmi_n[2] 79 -io_std SB_LVCMOS
set_io hdmi_n[1] 81 -io_std SB_LVCMOS
set_io hdmi_n[3] 136 -io_std SB_LVCMOS

// VGA OUT

set_io v_sync 97
set_io h_sync 76

set_io r_out[0] 91
set_io r_out[1] 95
set_io r_out[2] 96

set_io g_out[0] 75
set_io g_out[1] 74
set_io g_out[2] 73

set_io b_out[0] 87
set_io b_out[1] 88
set_io b_out[2] 90

// SOUND OR VGA ANALOG IN

set_io analog_in 56

// POTENTIOMETER IN

set_io pot_in 52

// KEYS IN

set_io key[0] 37
set_io key[1] 38
set_io key[2] 39
set_io key[3] 41
set_io key[4] 42
set_io key[5] 43
set_io key[6] 44
set_io key[7] 45
set_io key[8] 47

// LEDS OUT

set_io green_led 23
set_io red_led 24

// VGA IN

set_io rpi_hsync 34
set_io rpi_vsync 31

module vga_sync_test(
input wire clk_in,
input wire [8:0] key,
input wire rpi_vsync,
input wire rpi_hsync,
input wire analog_in,
inout pot_in,
output [3:0] hdmi_p,
output [3:0] hdmi_n,
output reg [3:0] r_out,
output reg [3:0] b_out,
output reg [3:0] g_out,
output wire h_sync,
output wire v_sync,
output wire red_led,
output wire green_led
);

wire display_en;
//reg [9:0] h_count;
wire [11:0] h_count;
//reg [9:0] v_count;
wire [11:0] v_count;

localparam h_pixel_max = 1280;
localparam v_pixel_max = 960;
localparam h_pixel_half = 640;
localparam v_pixel_half = 480;


reg [4:0] addr;
reg [7:0] data;
reg [7:0] data_out;
always@(addr) begin
case (addr)

0 : data = 0;
1 : data = 16;
2 : data = 31;
3 : data = 45;
4 : data = 58;
5 : data = 67;
6 : data = 74;
7 : data = 77;
8 : data = 77;
9 : data = 74;
10 : data = 67;
11 : data = 58;
12 : data = 45;
13 : data = 31;
14 : data = 16;
15 : data = 0;
16 : data = -16;
17 : data = -31;
18 : data = -45;
19 : data = -58;
20 : data = -67;
21 : data = -74;
22 : data = -77;
23 : data = -77;
24 : data = -74;
25 : data = -67;
26 : data = -58;
27 : data = -45;
28 : data = -31;
29 : data = -16;
default : data = 0;
endcase
end

reg[22:0] div_cntr1;
reg[22:0] div_cntr2;
reg half_sec_pulse;

always@(posedge clk_in)
begin
div_cntr1 <= div_cntr1 + 1;
if (div_cntr1 == 0)
if (div_cntr2 == 0)
begin
div_cntr2 <= 0;
half_sec_pulse <= 1;
end
else
div_cntr2 <= div_cntr2 + 1;
else
half_sec_pulse <= 0;

end


always @(posedge half_sec_pulse) begin

data_out <= data;
addr <= addr + 1;
if(addr == 29)
addr <= 0;

end

// FOR AUDIO IN INTERACTION
assign red_led = analog_in;
assign green_led = analog_in;

// FOR KEY INTERACTION key[8:0]

// FOR POT INTERACTION

reg [15:0] adc_count= 0; //16 bits to count how long it's taking to charge. 32,768 is the max value. 1 extra MSB bit for just discharging the cap.
reg [14:0] pot_value= 0; //to store cap charge time value
reg [14:0] final_pot_value= 0;

wire adc_in;
reg adc_sample = 1; //first time through we want to sample the cap value

wire adc;


assign pot_in = (adc_sample) ? 1'bZ : 1'b0;
assign adc_in = pot_in;

// for a 25MHz clock we divide 100MHz by 4
reg [1:0] clk_div = 0;

always @(posedge clk_in)
begin
clk_div <= clk_div + 1;
end


always @(posedge clk_div[1]) begin //25MHz clock

adc_count <= adc_count + 1; // start counting

if(adc_count>=16'b1000000000000000 )begin // once we have rolled over 15 bit counter...

adc_sample <= 1'b0; // ...discharge cap for a while to restart the process.

end

else begin

adc_sample<=1'b1; //put cap pin in high 'Z'

if(adc_in==1'b1) begin // if cap charged...

pot_value[14:0]<=adc_count[14:0]; //store this value in pot


end

end

end


// FOR SOUND INTERACTION

// FOR AUDIO IN INTERACTION

//Check if we can create RGB colors
always @(posedge clk_in) begin



if (display_en) begin
if (h_count < h_pixel_half + data_out
&& v_count < v_pixel_half - data_out) begin
//Assign here your test color



//pot changing colors
case(pot_value[14:13])

2'b00: begin //yellow
r_out <= 3'b010;
g_out <= 3'b110;
b_out <= 3'b011;
end
2'b01: begin //cyan
r_out <= 3'b011;
g_out <= 3'b100;
b_out <= 3'b001;
end
2'b10: begin //magenta
r_out <= 3'b110;
g_out <= 3'b110;
b_out <= 3'b011;
end
2'b11: begin //blue
r_out <= 3'b010;
g_out <= 3'b111;
b_out <= 3'b111;
end

default: begin // white
r_out <= 3'b010;
g_out <= 3'b010;
b_out <= 3'b011;
end
endcase




end else if (h_count > h_pixel_half - data_out
&& v_count < v_pixel_half + data_out) begin

if (analog_in == 1) begin
//Assign here your test color
r_out <= 3'b010;
g_out <= 3'b110;
b_out <= 3'b011;
end
else begin
r_out <= 3'b001;
g_out <= 3'b010;
b_out <= 3'b100;
end
end else if (h_count < h_pixel_half - data_out
&& v_count > v_pixel_half - data_out) begin
//Assign here your test color
r_out <= key[2:0];
g_out <= key[5:3];
b_out <= key[8:6];
end else begin
//Assign here your test color
r_out <= 3'b010;
g_out <= 3'b010;
b_out <= 3'b010;
end
end else begin
r_out <= 3'b000;
g_out <= 3'b000;
b_out <= 3'b000;
end
end

vga_sync vga_s(
.clk_in(clk_in), //12MHz clock input
.h_sync(h_sync),
.v_sync(v_sync),
.h_count(h_count),
.v_count(v_count),
.display_en(display_en) // '1' => pixel region
);

endmodule

module ram (din, write_en, waddr, wclk, raddr, rclk, dout);// 32768‬ x 2

parameter addr_width = 15; // to access all 32768‬ bits of the address
parameter data_width = 2;
input [addr_width-1:0] waddr, raddr;
input [data_width-1:0] din;
input write_en, wclk, rclk;
output reg [data_width-1:0] dout;
reg [data_width-1:0] mem [(1<<addr_width)-1:0]
;

always @(posedge wclk) // Write memory.
begin
if (write_en)
begin
mem[waddr] <= din; // Using write address bus.
end
end
always @(posedge rclk) // Read memory.
begin
dout <= mem[raddr]; // Using read address bus.
end
endmodule

addr <= (((hc-hbp)>>2)+(((vc-vbp)>>2)*160));

assign data_in[7:0] = (again_xnor[7:0] > key[7:0]) ? 8'b11111111 : 8'b00000000;

this :

if ((rec==0) && (a>=8'b10000000))

to this :
if ((rec==0) && (a==8'b00000000))

localparam h_pixel_total = 800;
localparam h_pixel_display = 640;
localparam h_pixel_front_porch_amount = 16;
localparam h_pixel_sync_amount = 96;
localparam h_pixel_back_porch_amount = 48;

localparam v_pixel_total = 525;
localparam v_pixel_display = 480;
localparam v_pixel_front_porch_amount = 10;
localparam v_pixel_sync_amount = 2;
localparam v_pixel_back_porch_amount = 33;

localparam h_pixel_max = 640;
localparam v_pixel_max = 480;
localparam h_pixel_half = 320;
localparam v_pixel_half = 240;

...


// for a 25MHz clock we divide the 100MHz clk_in by 4
reg [1:0] clk_div = 0;

always @(posedge clk_in)
begin
clk_div <= clk_div + 1;
end
...

vga_sync vga_s(
.clk_in(clk_div[1]), // giving vga_sync the 25MHz clock 
.h_sync(h_sync),
.v_sync(v_sync),
.h_count(h_count),
.v_count(v_count),
.display_en(display_en) // '1' => pixel region
);

endmodule

addr <= (((hc-hbp)>>1)+(((vc-vbp)>>1)*320));

...
else
begin
hc <= 0;
if (vc < vlines) begin
vc <= vc + 1;
screen_count <= screen_count + 1;
end
else
vc <= 0;
end
end
else begin
c0_high_speed <= {2'b00, c0_high_speed[9:2]};
c1_high_speed <= {2'b00, c1_high_speed[9:2]};
c2_high_speed <= {2'b00, c2_high_speed[9:2]};
clk_high_speed <= {2'b00, clk_high_speed[9:2]};
latch_high_speed <= latch_high_speed + 1'b1;
end
end

always @(posedge latch_high_speed[2]) // display 100% saturation colourbars
begin

case(screen_count[9])

1'b0 : multiplier = 1;
1'b1 : multiplier = 2;

default : multiplier = 1;

endcase

// first check if we're within vertical active video range
if (vc >= vbp && vc < vfp)
begin
// now display different colours every 80 pixels
// while we're within the active horizontal range
// -----------------
if(hc >= hbp && hc < hfp) begin

//pixel <= heart[(((hc-hbp)>>2)+(((vc-vbp)>>2)*160))];
addr <= (((hc-hbp)>>1)+(((vc-vbp)>>1)*320*multiplier));

...

...

case(key[7:6])
2'b00: multiplier = 1;
2'b01: multiplier = 2;
2'b10: multiplier = 3;
2'b11: multiplier = 1;

default: multiplier = 1;
endcase

if (vc >= vbp && vc < vfp)
begin

if(hc >= hbp && hc < hfp) begin

addr <= (((hc-hbp)>>1)+(((vc-vbp)>>1)*320*multiplier));

...

...

case(key[7])
2'b0: offset = 0;
2'b1: offset = 78000;
default: offset = 0;
endcase


if (vc >= vbp && vc < vfp)
begin

if(hc >= hbp && hc < hfp) begin

addr <= (((hc-hbp)>>1)+(((vc-vbp)>>1)*320)+ offset);

...

if (vc < vlines) begin
vc <= vc + 1;
frame <= frame + 1;
if(screen_count>12)begin
screen_count <= 0;
end
if (frame > 6000) begin
screen_count <= screen_count + 1;
frame <= 0;
end
end

...

addr <= (((hc-hbp)>>2)+(((vc-vbp)>>2)*160)+(offset*screen_count));

After failing to do various “simple” things in verilog, I’m doing a little refresher course. Resources :

• https://hackaday.com/series_of_posts/williams-icestick-tutorial/
• https://www.doulos.com/knowhow/verilog_designers_guide/
• https://vol.verilog.com/

//VERILOG CODING PRACTICES

//verilog is case sensitive !

reg THIS; // not the same as this !
reg this;

//to repeat : {repeat_count{}}

vec[1:20] = {4{5'b10110}};

**********

// this is better than just [23:0] for readability :
parameter buswidth = 24;
input [buswidth-1:0] bus;

//this is better than just 47:0 for readability :
reg [8*6:1] string6;

***********

//scalars (single bit vs vectors which are multi-bit) can have the following values:

0 - logic zero (false)
1 - logic one (true)
x - unknown value
z - high-impedance value

// therefore an equality test can return unknown if one of the operands is x or z !

if (expression) is evaluated :

0 false
1 true
x false
z false

//nets receive signal values
//net or register port expressions send values

//regs need initial conditions, wires need NOT to have initial conditions assigned.

//keep in mind if you're making combinational or sequential logic !

*******

//legal assignments :

lhs = rhs;
lhs[bit] = rhs;
lhs[partmsb:partlsb] = rhs;
{lhs1, lhs2} = rhs;
***********
//for a null operation use the semi-colon :

if (control)
;
else
x = f(y);

*******
//You can give names to binary combinations :

`define A 3'b001
`define B 3'b010
`define C 3'b100

initial state = `A;

********
//You can deassign :

else if (!preset)
assign q = 1;
else
deassign q;

*********

// in simulation you can use the $random system function

integer rand;
rand = $random;

*************
//don't do this :
assign n1 = w1 + f(w2) + g(w3);

//do this instead :
assign t2 = f(w2);
assign t3 = g(w3);
assign n1 = w1 + t2 + t3;

************
//this :
wire AB;
assign AB = A & B;

// can be written like this :
wire AB = A & B;

**************

//This creates an implicit sensitivity list that contains all the signals whose values are 
//read in the statements of the always block :

always @(*)

//Remember : To synthesize combinational logic using an always block, 
//ALL inputs to the design must appear in the sensitivity list.

********

// LATCHES 
// https://nandland.com/how-to-avoid-creating-a-latch/
//Latches are bad, they are combinational and not driven by a clock. If you use a clocked process 
//you avoid the possibility of unintentionally making a latch.

//All combinational processes need to explicit assignments for every possibility. Don't leave a conditional test
//that has only an if and no else to account for the other possible values.

// TEST BENCHES

//for test benches use # to make things happen at certain times :

x = 0;
#10 x = x + 1;
#20 x = x + 2;
#30 x = x + 3;
#20 x = x + 2;
#10 x = x + 1;

time:       value of x :
0                0
10               1
30               3
60               6
80               8
90               9

// for test bench clocks :
always
begin
#period/2 clk = ~clk;
end

// CLOCK BUFFERING 

Do external clocks need buffering ? If so, is this how to buffer an external clock ?

SB_GB_IO gb_io1 (
.PACKAGE_PIN( clk ),
.GLOBAL_BUFFER_OUTPUT( gclk )
);

...or with extra params ?

SB_GB_IO gb_io1
( .PACKAGE_PIN(clk),
.OUTPUT_ENABLE(1'b1),
.GLOBAL_BUFFER_OUTPUT(gclk)
);
defparam gb_io1.PIN_TYPE = 6'b000001;
defparam gb_io1.PULLUP = 1'b0;
defparam gb_io1.NEG_TRIGGER = 1'b0;
defparam gb_io1.IO_STANDARD = "SB_LVCMOS";

// MEMORY

// to instantiate 1 bit memory :
reg membits [1023:0]; // 1024 1-bit registers

//You can't take a bit-select or part-select of a memory element.
//Thus, if you want to get the 3rd bit out of the 10th element of a memory, 
//you need to do it in two steps:

reg [0:31] temp, mem[1:1024];
...
temp = mem[10];
bit = temp[3];

// RACE CONDITIONS 
// This code produces a 'race condition' :

always @(posedge clock) always @(posedge clock)
dff1 = f(x); dff2 = dff1;

// it can be fixed with non-blocking assignments :

always @(posedge clock) always @(posedge clock)
dff1 <= f(x); dff2 <= dff1;

//CROSSING CLOCK DOMAINS 

one solution is to double latch everything.

**********

I am systematically trying to figure out why I can’t take rpi input and redisplay it with the simple HDMI code.

I am starting by sending signals in a pass through way like this :

always @(posedge rpi_pixel_clock) begin

b_in_repeat <= b_in;

end

I get the same input signal but one clock later on the ‘scope so as expected.

 Thoughts on this as a product now that SD card seems possible :

• I could put “sprites” like the bechamel logo and some numbers in some location in memory.
• I could be able to save screen shots on the SD card with a button combo.
• Could there be a kind of database, which would be like how rhino saves files of 3D models one is working on ?
• Am I making a mini computer (ALU, slow big memory, fast SRAM, user interface, screen output) ? What do I think about a scroll wheel and a mini screen then ?
• What could I do with a stack of images from the SD card ?

Just a reminder of what a fully fleshed out video system looks like with the Gameduino : https://excamera.com/files/gameduino/synth/doc/gen/poster.pdf

*********

Checking-in with my project goals for 2024.

• This year the goal was to have a finished open-source project that could be shared with people online or as a kit/product via prepared instruments.com. I would be able to show it to students as an example of a finished design/engineering project that I have completed. The idea would be to stabilize the design, to stop making endless boards, and begin exploring more verilog codes that run on it.

Currently, the Cyber Campus version of the board is basically complete enough to transition into just trying new code. There is just the SD card that remains before the object has a feel of being an independent finished object that isn’t dependent on any other products (like rpi) to function.

Perhaps a distinction between the product, art and workshop kit would be useful :

Kit : reprogrammable, built around the rpi, solderable by beginners, etc.

Product : HDMI IN (a compromise would be that chip that handles everything like the TFP401PZP) and HDMI OUT, plug and play with modern tech. Has a larger FPGA to be able to do more cool stuff.

Art : The Cyber Campus version has everything I need to have fun with new codes, especially ones that interact with time and sequence (like temporal compression?), like differences between images in time impacting the kinds of transformations instead of staying with just static filters.

*********

I need to make the SD card code more generalizable with a function that takes CMD IN.

Here is the command format :

For example CMD8, the first byte is 01001000 with : 0 (start bit) + 1 (tx bit) + 010000 (six bits of the CMD number 8 in binary). After this are 32 bits of arguments (such as address you want to select) the 6 bit CRC7 and then 1.

NOTE ** I may need to change the speed from 50KHz to 100KHz or 200KHz for things to work. I am unclear about when I need to send ticks but forum user writes this :

; There must be 8 clocks after
; * a command with no response
; * the response of a command with a response
; * the end of a read data block
; * the CRC status token on a write

Here is the sequence of commands I have so far :

//TICKS
parameter TICKS = 48'b11111111_11111111_11111111_11111111_11111111_11111111;

//CMD0 “GO_IDLE_STATE”
parameter CMD0 = 48'b01000000_00000000_00000000_00000000_00000000_10010101;

//CMD8 “SEND_IF_COND”
parameter CMD8 = 48'b01001000_00000000_00000000_00000001_10101010_10000111;

//CMD55 “APP_CMD”
parameter CMD55 = 48'b01110111_00000000_00000000_00000000_00000000_01100101;

//ACMD41 “SD_SEND_OP_COND”
parameter ACMD41 = 48'b01101001_01000000_00010000_00000000_00000000_11001101;

//CMD2 “ALL_SEND_CID”
parameter CMD2 = 48'b01000010_00000000_00000000_00000000_00000000_01001101;

//CMD3 “SEND_RELATIVE_ADDR”
parameter CMD3 = 48'b01000011_00000000_00000000_00000000_00000000_00100001;

//CMD7 “SELECT/DESELECT_CARD”
parameter CMD7 = 48'b01000111_00000000_00000000_00000000_00000000_CRC+1; // need to generate my own CRC for this

//CMD17 “READ_SINGLE_BLOCK”
parameter CMD17 = 48'b01010001_00000000_00000000_00000000_00000000_CRC+1; 

NOTE ** There is a read multiple block command CMD18 READ_MULTIPLE_BLOCK that takes a 32 bit address and continuously transfers data blocks until interrupted by the STOP_TRANSMISSION command. By default sends 512 bytes followed by a CRC.

I am currently breaking up the code into cycles of 48 clock pulses to send and receive commands in sequence.

counter <= (counter==47) ? 0 : counter+1; // to count the steps in the sending of a single CMD
phase <= (counter==47) ? phase+1: phase; // to count how many CMDs we have sent

Each command is currently sent in order by checking the phase. For example :

if (phase == 8) begin
      rec <= 1; // set CMD to output
      CMD <= ACMD41[counter]; // iterate through the 48 bit command
end

Listening to input is tougher because of my poor understanding of inout, I am using inout to define the CMD pin. If we are receiving it is put in a high Z state.

assign CMD = rec ? CMD : 1'bz;

I am not sure if this will work :

if (phase == 9) begin
      rec <= 0; // set CMD inout pin to high Z
      data_in[counter] <= CMD; //store the data in data_in
end

Here I’m trying to check if a ready bit 31 is still unset :

if ((data_in & (1<<31))==0)

Here I’m trying to compose the CMD7 by concatenating the appropriate bytes.

//CMD7 “SELECT/DESELECT_CARD”
if (phase == 16) begin
   rec <= 1;
   RCA[15:0] = data_in[31:15]; // retrieve the RCA from the previous response
   CMD7[47:0] = {8'b01000111,RCA[15:0],16'b0000000000000000,CRC+1}; // compose CMD7 from parts
   CMD <= CMD7[counter]; // send the command
end

****

I’m on this site to calculate the CRC7 (https://www.ghsi.de/pages/subpages/Online%20CRC%20Calculation/)

• First I enter the CRC polynomial which for the SD card is x7 +x3 + 1
• Then I translate the 5 bytes I want to send into hex
• The 7 bit value generated at the end of the page is then added to the end of the message plus the end bit (1)

I need to figure out how to incorporate the CRC in verilog for certain commands however :

The above website automatically generates this verilog code that takes one bit at a time :

// ==========================================================================
// CRC Generation Unit - Linear Feedback Shift Register implementation
// (c) Kay Gorontzi, GHSi.de, distributed under the terms of LGPL
// ==========================================================================
module CRC_Unit(BITVAL, BITSTRB, CLEAR, CRC);
input BITVAL; // Next input bit
input BITSTRB; // Current bit valid (Clock)
input CLEAR; // Init CRC value
output [6:0] CRC; // Current output CRC value

reg [6:0] CRC; // We need output registers
wire inv;

assign inv = BITVAL ^ CRC[6]; // XOR required?

always @(posedge BITSTRB or posedge CLEAR) begin
if (CLEAR) begin
CRC = 0; // Init before calculation
end
else begin
CRC[6] = CRC[5];
CRC[5] = CRC[4];
CRC[4] = CRC[3];
CRC[3] = CRC[2] ^ inv;
CRC[2] = CRC[1];
CRC[1] = CRC[0];
CRC[0] = inv;
end
end

endmodule

I am not sure exactly how to feed this module one bit at a time. I also feel unsure about how to properly incorporate modules from different files.

****

Here is my test code (once the timescale is uncommented) that I’m hoping will not require CRC (I’ll just look on the oscilloscope to see what the RCA is and then use that). It is the simplest possible setup.

Possible things that need changing :

• I am not waiting to see if bit 31 is set after sending ACMD41, so I probably will need to add a delay here ? *EDIT* I am getting a busy bit 31 the first time I ask at the moment.
• 8 clock ticks instead of 48 ? *EDIT* DONE
• No clock ticks after certain commands?
• The RCA (and CRC) if it is not 0001
• The block address (and CRC) if it is not 0

//-----------------------------------------------------------------
// - Attempt at SD 1 bit communication -
//CMD0 “GO_IDLE_STATE”
//CMD8 “SEND_IF_COND”
//CMD55 “APP_CMD”, ACMD41 “SD_SEND_OP_COND” with argument 40100000 (HCS=1, voltage = 3.3).
//The R3 response has HCS and the supported voltages set. Repeat until bit 31 of the response is 1.
//CMD2 “ALL_SEND_CID” with argument 00000000. The R2 response has the CID. I ignore it.
//CMD3 “SEND_RELATIVE_ADDR” with argument 00000000. The R6 response contains the RCA and some status that I ignore.

//The card is now in the stand-by state. Reading a block is accomplished by
//CMD7 “SELECT/DESELECT_CARD” with argument bits 31-16 = the RCA you were given, 15-0 = 0. The R1b response I ignore.
//CMD17 “READ_SINGLE_BLOCK” with argument = the block address.
//The R1 response I ignore, but there will also be the block data.
//Keep toggling the clock, and you’ll eventually see a start bit followed by a block of data and a CRC.
//-----------------------------------------------------------------

`default_nettype none // disable implicit definitions by Verilog
//`timescale 1us/1ns

module top(
input wire clk100,
input wire reset,
//input reg DAT,
output reg SCK,
output reg CMD
);

//CMD0 “GO_IDLE_STATE”
parameter CMD0 = 48'b01000000_00000000_00000000_00000000_00000000_10010101;

//CMD8 “SEND_IF_COND”
parameter CMD8 = 48'b01001000_00000000_00000000_00000001_10101010_10000111;

//CMD55 “APP_CMD”
parameter CMD55 = 48'b01110111_00000000_00000000_00000000_00000000_01100101;

//ACMD41 “SD_SEND_OP_COND”
parameter ACMD41 = 48'b01101001_01000000_00010000_00000000_00000000_11001101;

//CMD2 “ALL_SEND_CID”
parameter CMD2 = 48'b01000010_00000000_00000000_00000000_00000000_01001101;

//CMD3 “SEND_RELATIVE_ADDR”
parameter CMD3 = 48'b01000011_00000000_00000000_00000000_00000000_00100001;

//CMD7 “SELECT/DESELECT_CARD”
parameter CMD7 = 48'b01000111_00000000_00000001_00000000_00000000_11011101; // ASSUMING RCA IS 0001

//CMD17 “READ_SINGLE_BLOCK”
parameter CMD17 = 48'b01010001_00000000_00000000_00000000_00000000_01010101; // ASSUMING ADDR ZERO EXISTS

//CMD18 “READ_MULTIPLE_BLOCK”
parameter CMD18 = 48'b01010010_00000000_00000000_00000000_00000000_11100001; // ASSUMING ADDR ZERO EXISTS


//some counters
reg [9:0] counter=0;
reg [9:0] phase=0;
reg [7:0] q=0;


// divide 100MHz clock by 255 to equal 196.0784315 KHz which is in the 100KHz - 400KHz range

always @(posedge clk100) begin

q <= q+1;
if(q == 0) begin
SCK <= ~SCK;
end
end

//to count 48 SCK cycles and also how many which step of the communication sequence we're on


always @(posedge SCK) begin


//send 8 ticks
if (phase == 0) begin

counter <= counter+1;

if (counter <= 7) begin
CMD <= 1'b1;
end
else begin
counter<=0;
phase<=phase+1;

end
end

//send CMD0

if (phase == 1) begin

counter <= counter+1;

if (counter <= 47) begin
CMD <= CMD0[47-counter];
end
else begin
counter<=0;
phase<=phase+1;

end

end


//send 8 clock ticks while CMD high

if (phase == 2) begin

counter <= counter+1;

if (counter <= 7) begin
CMD <= 1'b1;
end
else begin
counter<=0;
phase<=phase+1;

end

end

//send CMD8


if (phase == 3) begin

counter <= counter+1;

if (counter <= 47) begin
CMD <= CMD8[47-counter];
end
else begin
counter<=0;
phase<=phase+1;
end


end


//set CMD to input

if (phase == 4) begin


counter <= counter+1;

if (counter <= 47) begin
CMD <= 1'bz;
end
else begin
counter<=0;
phase<=phase+1;

end


end



//NEED THIS ? send 8 clock ticks while CMD high

if (phase == 5) begin

counter <= counter+1;

if (counter <= 7) begin
CMD <= 1'b1;
end
else begin
counter<=0;
phase<=phase+1;

end

end

//send CMD55


if (phase == 6) begin

counter <= counter+1;

if (counter <= 47) begin
CMD <= CMD55[47-counter];
end
else begin
counter<=0;
phase<=phase+1;

end



end

//listen to response

if (phase == 7) begin

counter <= counter+1;

if (counter <= 47) begin
CMD <= 1'bz;
end
else begin
counter<=0;
phase<=phase+1;

end


end


//NEED THIS ? send 8 clock ticks while CMD high

if (phase == 8) begin

counter <= counter+1;

if (counter <= 7) begin
CMD <= 1'b1;
end
else begin
counter<=0;
phase<=phase+1;

end

end

//send ACMD41


if (phase == 9) begin

counter <= counter+1;

if (counter <= 47) begin
CMD <= ACMD41[47-counter];
end
else begin
counter<=0;
phase<=phase+1;

end

end

//listen to response and check bit 31 is 1

if (phase == 10) begin


counter <= counter+1;

if (counter <= 47) begin
CMD <= 1'bz;
end
else begin
counter<=0;
phase<=phase+1;

end

end


//send CMD2

if (phase == 11) begin

counter <= counter+1;

if (counter <= 47) begin
CMD <= CMD2[47-counter];
end
else begin
counter<=0;
phase<=phase+1;

end


end


//listen to 136 bit CID CMD from SD

if (phase == 12) begin

counter <= counter+1;

if (counter <= 135) begin
CMD <= 1'bz;
end
else begin
counter<=0;
phase<=phase+1;

end

end


//send CMD3

if (phase == 13) begin

counter <= counter+1;

if (counter <= 47) begin
CMD <= CMD3[47-counter];
end
else begin
counter<=0;
phase<=phase+1;

end

end

if (phase == 14) begin

counter <= counter+1;

if (counter <= 47) begin
CMD <= 1'bz;
end
else begin
counter<=0;
phase<=phase+1;

end

end

//CMD7 “SELECT/DESELECT_CARD”
if (phase == 15) begin


counter <= counter+1;

if (counter <= 47) begin
CMD <= CMD7[47-counter];
end
else begin
counter<=0;
phase<=phase+1;

end

end

//listen to CMD from SD

if (phase == 16) begin


counter <= counter+1;

if (counter <= 47) begin
CMD <= 1'bz;
end
else begin
counter<=0;
phase<=phase+1;

end

end

//CMD17 “READ_SINGLE_BLOCK” with argument = the block address.

if (phase == 17) begin



counter <= counter+1;

if (counter <= 47) begin
CMD <= CMD17[47-counter];
end
else begin
counter<=0;
phase<=phase+1;

end

end

if (phase == 18) begin



counter <= counter+1;

if (counter <= 47) begin
CMD <= 1'bz;
end
else begin
counter<=0;
phase<=phase+1;

end

end

// Should start to see data coming in on the DAT pin !!
if (phase >= 19) begin

// DAT pin

end


end

endmodule

The sequence for ModelSim was :

For my first finished product for prepared instruments (preparedinstruments.com), the goal is to remake the hardware 7ch palimpsest.OS SRAM but with :

• a square keyboard grid interface like the PEW design (knobs and switches replaced with keys)
• an aluminium PCB substrate (with a single-sided board) ?
• a simpler amp in path with only one pot
• all 0805 and SOIC packages

I’ve been thinking about it and I can’t say that this board will be inexpensive. If you want to explore video synthesis inexpensively, you should do things for free in code on the computer. This is a physical digital logic / analog device so it will cost money.

Because it’s the first in a series, I would like this board to set the format of the others. I’m imagining them all like Ritter Sport square bars. Like the eurorack format, I would like to have a standard way of powering the boards and I need to decide on a way of jumping between the boards (VGA cables?).

I’d also like the boards and the packaging to be ecologically responsible. I don’t know if this means using an aluminium substrate (which can be easily recyclable in theory) or a flexible circuit (with either a thin plastic or stained steel stiffener – in theory recyclable).

Looking back on the synths from this year, I never really wanted to code/configure the things I made. Doing hardware synths makes sense as it puts me in a different spot in the market place, makes the designs harder to just copy, and it allows me to savour the suffering in the design process. The analog function board was ultimately underwhelming. Going the direction of installation pieces isn’t satisfying because they are too site-specific and local for my project I feel (though perhaps making films is the solution here). The gameboy design made me feel bad about the waste of buying a mini screen and the software challenge of communicating with it seems not crucial to my project (but I will finish at least the physical side of the project to test the layout). The memory boards were the coolest, and of them the layering board is the most elegant design and the most interesting in what it can do.

Here’s the new site where the béchamel will appear:

Thoughts from Vincent :

• Connect with other people making video synths !
• Try shooting some of your own film to put through the machines !
• What is it you are trying to SAY ? Hmm

What is it you are trying to SAY:

I think I’m trying to say with this project is : Look at what I like doing, isn’t it fun and cool/silly/odd what is to be found ?!  More specifically, to share the preliminary results of my creative research project method. The project I guess is trying to say that it is possible and fun to a embark on an explorative creative process with technology at a low level (and not just use pre-packaged tech things) with some of the wrestling with constraints that that requires. I like that the objects are idiosyncratic, playful compositions but also that they are ornately routed and articulated. I like the message that machines can look different, and be more human and odd ? I guess I’m also trying to have fun with the ideas of usefulness and futility, so it is partially supposed to be humorous? I like the détournement of industrial objects for playful means, the implication that old things can be exciting and that deconstructing a system reveals unexpected inner worlds. I like that the deconstructing of machines is also the deconstructing of how they interact with our world, like the data they save and how they represent our information.

Thinking that Alterity, oddity, idiosyncracy and animism in objects and people and culture I think are totally up there. This was a fascination of my dad’s.

To echo some artists’ quotes that resonate :  “I don’t know what I’m looking for until I see it.” (Cindy Sherman)

“The reason I play so many sounds, maybe it sounds angry, is because I’m trying so many things at one time, you see? I haven’t sorted them out. I have a whole bag of things that I’m trying to work through and get the one essential.” (John Coltrane)

 I want to learn things all the time, I want to understand the patterns behind things. I experience science through craft. With craft I try to cultivate sensitivity in a practiced, purposeful way. If you work with marbling you know just as much about viscosity and flow than a scientist, through your fingertips in a different way. (Tauba Auerbach)

Try shooting some of your own film to put through the machines?

I started thinking about what I would want to film and how. I thought about the beautiful cinematography I appreciate in special films like The Souvenir I & II. I think it would be cool to shoot some video because I spend a lot of time watching videos (not the case for writing because I don’t do enough reading). I thought about recording things I see on commutes, and about the forest walk in Saclay. This has made me consider that what I find interesting about the electronics side is memory, more than just modifying things with math. How the computer represents our world is mainly impacted by its ability to remember it. I’m starting to think that this project could be about memory, putting my own memories into the computer memory. I’m thinking about Iain and Brian’s film Lifesaver and the impact it’s had on me. Also Iain’s photography in general, especially his black and white stage.

I think DRAM board could be a cool project because of how inexpensive large memory is and the memory degradation which could be really poetic in a project about memory. This goes back to Paolo’s suggestion to make a project around an image put into UV erasable EEPROM and watching it slowly degrade in the sun.

I’ve been thinking about how to record as well, with a gopro discretely or with my G2 Cannon more deliberately. I also think that humor should be the primary part of my shooting, not some wanna-be poetic stuff.

**********

Trying to design the interface :

Might need latched buttons like this :

Some all metal heavy duty toggle switches look cool in an array but I’m worried toggle switches will require too much force to turn on and will therefore be annoying all arrayed together on a tiny board.

The other option is to stick with tactile buttons and to convert them into on/off buttons with a JK flipflop. When J and K are pulled high, the outputs Q and !Q toggle every time the clock rises (once per push). This would mean I could have an LED turn on when you push too (helps in the dark for performances!) but I wouldn’t have the pushed-in versus fully extended visual feedback from the button and it would add ICs to my packed board.

I am considering doing this on two boards, the top one would be a single-sided aluminium board which would look cool but also make the top interface more durable. This board would have the leds, keys, JK flip flops. The board below could have lots of space to be laid out in a relaxed, rational way without having to dodge buttons. I could enclose it in a little box or I could leave the two boards exposed on one side or all around.

This follows from the constraint that this will be a real product. I don’t want to make a super difficult to solder and debug highly compact circuit. I want to keep things easy to repair. It also makes the device modular, I could switch a new keyboard and keep the base circuit or vice versa. I would like to keep this device affordable and not using rare / exotic components. I’m more in the robust, standard design world now that Tommy is good at working with perhaps.

*******

I just cleaned by apartment and went through my lab equipment. I will be sending tens of boards and plastic bags to the recycling which makes me sad. I would like to avoid finding myself in this situation in the future.

Check out this Soviet-developed visual programming language DRAKON (https://en.wikipedia.org/wiki/DRAKON)

It would be cool to make a flow diagram like this for the FPGA code I’ve already made.

Also this automation representation called GRAFCET (https://fr.wikipedia.org/wiki/Grafcet)

*******

Check out these user interface principles (https://en.wikipedia.org/wiki/User_interface_design):

• Clarity: the information content is conveyed quickly and accurately.
• Discriminability: the displayed information can be distinguished accurately.
• Conciseness: users are not overloaded with extraneous information.
• Consistency: a unique design, conformity with user’s expectation.
• Detectability: the user’s attention is directed towards information required.
• Legibility: information is easy to read.
• Comprehensibility: the meaning is clearly understandable, unambiguous, interpretable, and recognizable.

********

Just watched a Youtube video by Code Aesthetic called Don’t Write Comments. The implication is that the code should be so readable that you don’t need to comment it. (He organizes code in such a way that the high level architecture comes through and if you want to get into the details you can check out individual functions). I’m trying to do something similar with the interface, have it be directly readable without text just based on color, button size and location.

I like the idea of being more pragmatic with the design and less obsessive about composition. The cut away in the top board could be nice because it show which color bits are going from rpi to the memory.

The question of the colors is tough – RED is for recording ? Should colors follow RGB ? What colors for clock division, and for selecting between MSB and LSB ? What about the LEDs versus the buttons ? EDIT : I’ve sinced moved to greyscale…

****

Being creative in different ways : Apollonian (rational thinking, order, logic, prudence and purity) vs. Dionysian (irrationality, chaos, passion, emotion and instinct). Electronics and logic circuits are clearly Apollonian, and the effects they create on screen are more Dionysian.

****

Looking into code bloat I learned the Unix philosophy of “do one thing and do it well”. Other programming credos :

• less functionality (“worse”) is a preferable option (“better”)’https://en.wikipedia.org/wiki/Worse_is_better)
• “Keep it simple, stupid!” (https://en.wikipedia.org/wiki/KISS_principle)
• rule of least power is a design principle that “suggests choosing the least powerful [computer] language suitable for a given purpose” (https://en.wikipedia.org/wiki/Rule_of_least_power)
• a simple (low complexity) solution to a problem of high complexity is seen as elegant. (https://en.wikipedia.org/wiki/Elegance)

**********

New Prepared Instruments github : https://github.com/preparedinstruments/bechamel

OK, here’s the final version of the boards. I will finally be able to test the one-sided aluminum surface reversed with buttons going through-hole. This is (my first) double-board design, keyboard on one and memory on the other with a ribbon jumping between them. This sampler will have two bits of data for the videos which will be new. Layers will now have different colors associated with them. The gen lock turned out to not be what I thought it was so I’m trying to sync by using V and H syncs (and their inverses) connected to the 590 freq division somehow (either to OE, CLR, or RCLK). I like this new setup to select different bits of the RPI. Cool things here are the double use of the buttons in momentary and latched mode with led indicators. New in this version will also be the triple diode packages for the VGA out.

I’ve taken my favorite interface and mixed it with my favorite circuit, let’s see how it works out ! At least I got to use up a bunch of components I already had lying around. Though, I have to say that no one could pay me enough money to assemble one of these myself, and despite my best efforts it is not minimal and easy to put together. Another issue is the fact that I don’t have the skill of imagining what “customers” want, I seem to be more focused on what I want. Does that make me a wanne-be artist as opposed to a wanna-be designer ?

And some renderings :

**********

Having a think about what my hardware synths could do better than computers. There is the tangible interface, and the speed and fixed-low latency of using hardware to manipulate data instead of software. While I was once again looking into what I can do with a simple FPGA I came across :

• this Elphel NC393 camera device board for handling multiple video streams using an FPGA https://wiki.elphel.com/wiki/File:Nc393-dev-sm.jpeg. Combining multiple video streams, or overlaying, sounds like an application? But in VGA you can do this with just a pot !
• User Jeremy from eevblog’s comment about FLIR explaining that they use FPGAs in order to do “spatial (across pixels) and temporal (across time) filtering simultaneously”.
• video transcoding from one resolution ‘https://en.wikipedia.org/wiki/Transcoding)
• real-time edge detection
• Mister FPGA video game console has a bunch of retro CRT scanline filters here https://boogermann.github.io/Bible_MiSTer/getting-started/extras/video-filters/
• FPGA student projects from this Cornell class : http://people.ece.cornell.edu/land/courses/ece5760/FinalProjects/

********************

I think that this project is becoming about memory, and possibly the parallels between human memory and computer memory. I wonder what role the FPGA would have here. Would it be positioned in between the video input and the memory to act as a kind of variable filter ? I can imagine an interface that would allow you to select between many different filters by moving your hand like on a theremin or an array of trackballs?

*****

Check out this visualization of randomness :

****

First feedback : it needs HDMI – Sam

This Texas Instruments TFP410PAP is back in stock at Mouser and seems easy enough to integrate onto the board at 8euros. It can be controlled without I2C so it could be connected directly to the raspberry pi DEN, HSYNC, VSYNC, color data.  Black Mesa Labs did a board using this IC here : https://blackmesalabs.wordpress.com/2017/12/15/bml-hdmi-video-for-fpgas-over-pmod/

I also found a VGA to HDMI converter on amazon : FOINNEX Adaptateur VGA vers HDMI avec Audio, Convertisseur VGA a HDMI Vieux PC vers TV Moniteur, 1080P VGA to HDMI Adapter pour Anciens Ordinateur 

TI also makes the TFP401x TI PanelBus™ Digital Receiver so I could have HDMI IN and HDMI OUT with the addition of 15 euros of chips…The alternative is to learn to do this with the FPGA.

*****

Check out these snazy metal container for this synth circuit :

https://store.synthrotek.com/Division-6-Business-Card-Synthesizer-PCB-and-IC_p_829.html

Check out this beautiful project Sam sent my by Jurg Lehni which compares different screen technologies : https://juerglehni.com/works/four-transitions

******

Thinking about modularity. If I wanted to have a signal chain with filters etc before the memory. I would need a way of daisy-chaining the power, and a way of patching cables between modules. I want it such that the thing functions with just one module but also can with multiple modules too.

Would the video in/out have to be HDMI to be in line with modern VJ practice ? Found some Chinese chips that do HDMI to VGA like the Lontium LT8511A and the Quintile CH7101B. I guess I would need one of these plus an HDMI out chip for each board for them to be truly modular.

I am thinking right now of a simple custom filter like the one in Photoshop (Nice explanation here : https://ian-albert.com/old/custom_filters/) accomplished with an FPGA and some kind of cool interface (track ball matrix ? capacitive touch array ?) :

***************

Check out this company OKW that makes cool modular knobs just outside of Paris : https://www.okw.fr/fr/Boutons-de-commande

**************

Working with the array of simple, robust, electronic components (switches, knobs, linear pots, track balls, etc.). Trying to think about how they could be daisy-chained together.

****************

Received and soldrerd PCBs !

• The aluminum layer can be engraved ! I could put “bechamel” on it !
• The standoff holes are too small for standard size.
• The boards are not perfectly the same dimensions.
• Perhaps I should have chosen white for the FR4 board instead of green
• No caps on the keyboard board
• Blurg, soldering components on the aluminum board without a heated plate is near impossible. I could have at least selected bigger format ICs.
• The latched keys which are connected to the output buffer enables aren’t really useful. They should be constantly on as the amp can always be just turned down to turn off the channel.

ERRATA MOTHERBOARD :

• From now on I think I will solder with a stencil and an oven, it’s too much work to solder manually.
• The latched keys don’t activate the same channels via buffer that they activate via AND gate to analog switch SEL.
• Also the text BLU, RED etc next to the knobs isn’t really accurate
• Should have VCC and GND on the silkscreen next to keyboard jumper
• Pin 13 and 11 of the 590 should by default be connected together on the next board
• I replaced the caps at the VGA out with 0ohm jumpers because I couldn’t see anything passing through on the oscilloscope
• I should add the turn off switch for rpi
• I am considering getting rid of the integrated rpi, despite its advantages, for a more straightforward HDMI IN or VGA IN. It adds considerable thickness to the board with the bulky 40 pin jumper situation and the fact that it is headless makes debugging a real pain.

ERRATA KEYPAD :

• I’m not sure the idea of using the aluminium sided boards really works, it’s all a bit too risky in terms of short circuits and it’s a real pain to solder (I need a heated plate, a nice microscope, loads of flux and a soldering iron). Fabien’s suggestion is to make the holes larger, so there is little risk of the pins touching the aluminium substrate, and then wiring flexible wire to make the necessary connections. Perhaps add some glue to keep the keys in place and move all the circuitry to the reverse side of the motherboard.
• Fabien had the idea of using the square holes of the mechanical switches possibly to mount them in the metal, perhaps they would even clip into place ?
• I roasted the ICs during soldering I think, the LEDs and JK latches are not working as expected.
• The added height for the two female ribbon cable connectors butting up against each other is insane. If it’s possible to just plug one board directly into the other you can achieve some nice compact sandwich board.
• Once again the 2mm standoff holes are too tiny
• The slot is perfect and the LEDs passing through the holes works as expected (though I should really use insulation on the two legs).

**************

Could I use coils from floppy disk player in a matrix as capacitive touch array ?

Could I make a super low resolution LED monitor to replace the HDMI IN and HDMI OUT DSLR field monitor ? (https://www.amazon.fr/Feelworld-Moniteur-Monitor-1920×1080-Peaking/dp/B07J5C98NW/ref=sr_1_1_sspa?crid=2SJEJTOJ1C6HB&keywords=Cam%C3%A9ra+Moniteur+DSLR&qid=1707557998&s=electronics&sprefix=cam%C3%A9ra+moniteur+dslr+%2Celectronics%2C89&sr=1-1-spons&sp_csd=d2lkZ2V0TmFtZT1zcF9hdGY&psc=1) :

I could also just use the simple rpi 5″ HDMI screen.

Other connection options if I had HDMI out :

Would it be smart to keep a VGA out as a plan B if ever the HDMI stopped working ?

It would be super useful to have a micro usb out to power the portable screen / pico projector. If so not much space left, would need to maybe bring the USB C power cable to the rpi side.

*************

Check out Jim Campbell’s low res display :!

References to reconstructing memories from the mind too !

***************

Setting up another rpi to loop VLC videos. I used primarily this tutorial: https://forums.raspberrypi.com/viewtopic.php?t=17051

First off, I kept the language as english to simplify things (despite having a french keyboard). I believe I did the rpi Lite installation (and then downloaded VLC?) but I’m not 100% sure.

In the place of

nano /home/pi  I have my user name :

nano /home/marrs

I also needed to go to View > Show Hidden to see the .config file then autostart then autovlc.desktop

nano /home/marrs/films/.config/autostart/autovlc.desktop

NOTE : This can’t be a text file, easiest way is to create the file directly in the terminal to avoid any problems as explained here :https://learn.sparkfun.com/tutorials/how-to-run-a-raspberry-pi-program-on-startup/method-2-autostart

I put this in the file (there is nothing else there)

[Desktop Entry] 
Type=Application
Exec=vlc --loop --fullscreen /home/marrs/playlist.m3u

Then control+O to save the file
 I put the m3u playlist here : home/marrs/playlist.m3u

*************

A new vision for this project : it’s a lo-fi device that takes HDMI and outputs HDMI but allows all kinds of very low res transformations like super low resolution GIFs, and saving every Nth frame of a film.

****TESTING ***

• Get sync sorted on this board. **EDIT** Unfortunately taking HSYNC, VSYNC and their inverses, and sending them to the 590 on various pins is not syncing the video. Thinking back, I think I managed this only when I was ANDing a bunch of freq divisions and then inverting the output to record images only every nth frame. *EDIT* OK I’ve got something taking VSYNC as the freq and the AND’ind the outputs to be used to reset the 4040 counters.
• Test the keyboard interface experience. ***EDIT** oof this is painful to do with jumpers and breadboards. Everything seems to be very sensitive to wierdness. It makes me want to eliminate the double board concept and just stick with hard soldered stuff on a single board. In the moments when things were briefly working it was super cool to control things with the keyboard.
• See what other video distortion is possible with the circuit
• I tried out the new HDMI converter, it works well.
• I figured out that you can save a multicolor multichannel image by recording on several channels at once !
• I like the idea of avoiding mission creep – not going into the screen or video codec business but instead staying with the theme of the project : video memory recording and playback.
• I like the idea of emphasizing how little memory there is here (4MB), and how I am trying to use every part of the bison rather than going for more memory.
• the new board should have usb micro female plugs to power an rpi, a VGA to HDMI converter, or the 5″ HDMI screen.
• No more connectors between boards that are mirrored… Thinking of a single-sided board where the buttons relate the the function (latched push button for things that need to be latched like the freq sel) keyboard keys for selecting layers to record to. I thought that having an array of the same button would make things clean but it ends up being confusing what button does what. I like the idiosyncratic and non orthogonal matrix approach.
• Just realized that I only need the single pole analog switch and don’t need the double pole anymore.
• I have higher quality pots I could use for smoother action

Super cool to see everything on the tiny screen actually (but when I plugged in everything from the v synth I think it went above the fuse limit so I’ll have to FIX THIS IN THE NEXT VERSION if I want all to be powered by the board):

*

Trying to make a list of cool new video distortions possible with this board :

• RCK and CLK of 590 could be connected to different frequencies
• could have two different counter pairs for two memories that could be desynchronized

**********

A quick redesign :

• Different components for different functions that they control (flat pots for inputs)
• Added DIP switches to turn on and off diff V SYNC divisions going to 4040 counter reset
• Only two speed buttons now, and they are physically latched
• Nicer quality top facing pots
• HDMI in and out with TI chips
• got rid of some replaceable components
• two micro USB connections to allow for these options :

*****

Trying out some hyper symmetrical design here.

Some considerations :

• Leaving enough room to be able to comfortably twist the knobs
• having mechanic keys close to one another so that they can be easily tapped with adjacent fingers
• associating each key with it’s respective knob spatially and clustering controls that are thematically related (like the dip switch and the two frequency setting pushbuttons which are both temporal)
• components that extend beyond the board on the top and bottom leaving room for hands on the keys and knobs
• Tommy thinks it should be hand held.

And a more controller-like option :

*******

Check out Vincent Rioux’s muq machine and how he show the grid of screen shots :

***

I want to make videos like this guy makes experimental sound sets :

****

I’m going to remake the keyboard board (but on FR4, with connector aligned to motherboard, no latched colors to activate channels) and add the sync lock functionality. This will allow me to finish that project and test it easily.

The videos I have already of the board functioning are cool : diff colors allow for multiple images to share the same frame and be legible. The freeze frame(s) is very cool and being able to freeze different chunks of time I think will add a lot of things to test.

After this board I’ll move back to FPGA as they represent the future of the project I think (also the NO SCHOOL workshop this summer). Before I make I new board I should play more with the FPGA SRAM boards I have already made. Can I , for instance, reproduce the bechamel board with an FPGA? Perhaps it is time to upgrade to an FPGA with more LUTs, even if it is harder to solder in Ball Grid Array packaging (and then why not SRAM in BGA also), and the HDMI helper chips.

The dream would be able to throw 20 of the new boards in the oven and have them all work at the end. I could then send them to friends around the world ! Would be clever to use capacitive touch in this case to avoid needing a physical interface like so : https://github.com/stnolting/captouch.

I could also design a silicone ruber keypad for it ! https://en.wikipedia.org/wiki/Silicone_rubber_keypad

Looks like an ESP32 with SD card can generate video as input, that or a rpi integrated into the board.

This might be one of those “already solved” problems which isn’t that much fun to explore…

***

Next steps for the HX8K board :

1. FFMPEG can output into monob or monow 1 bit pixel format and different dimensions. Test making a low resolution video and putting it on an SD card and having Arduino read it and transfer it to FPGA on the gameboy console board I made. (This will test if can replace rpi or HDMI IN with SD card in on next board)
2. Try again to see if HDMI out is possible with FPGA using the two boards I made to test this. (This will decide if need an HDMI helper chip or not on next board)
3. Try to use internal FPGA BRAM to save a screenshot on the Villette Makerz board. (This will test if need SRAM or not on the next board).
4. Replace mechanical keys with capacitive touch so everything is as light as possible.
5. Plan to get JLC PCB to assemble it ?

****

New top board, no longer aluminum, no more LEDs, which has the V SYNC ADD circuitry, debounced keys, and a female header to connect directly to the motherboard.

*****

Realized that I haven’t used the BRAM on the FPGA and that I could store low res recordings there. *EDIT* But it’s only 64K in total for the HX1K which is very little space. Probably more useful to store a mini buffer before sending it along to the SRAM. I’ve tried to create BRAM primitives in IceCube but it’s not working so far. This code from TinLethax appears to work in IceCube :

module BRAM(
input R_CLK,
input W_CLK,

input [7:0]BRAM_IN,
output reg [7:0]BRAM_OUT,

input [11:0] BRAM_ADDR_R,
input [11:0] BRAM_ADDR_W,

input B_CE_W,
input B_CE_R);

reg [7:0] mem [3003:0];

always@(posedge R_CLK) begin// reading from RAM sync with system clock 
if(!B_CE_R)
    BRAM_OUT <= mem[BRAM_ADDR_R];   
end 

always@(posedge W_CLK) begin// writing to RAM sync with Slave SPI clock.
if(!B_CE_W)
    mem[BRAM_ADDR_W] <= BRAM_IN;
end

endmodule

 module ram (din, addr, write_en, clk, dout);// 512x8
parameter addr_width = 9;
parameter data_width = 8;
input [addr_width-1:0] addr;
input [data_width-1:0] din;
input write_en, clk;
output [data_width-1:0] dout;
reg [data_width-1:0] dout; // Register for output.
reg [data_width-1:0] mem [(1<<addr_width)-1:0];

always @(posedge clk)
begin
if (write_en)
mem[(addr)] <= din;
dout = mem[addr]; // Output register controlled by clock.
end
endmodule 

set_io hdmi_p[0] 139 -io_std SB_LVCMOS
set_io hdmi_p[2] 78 -io_std SB_LVCMOS
set_io hdmi_p[1] 80 -io_std SB_LVCMOS
set_io hdmi_p[3] 137 -io_std SB_LVCMOS

set_io hdmi_n[0] 138 -io_std SB_LVCMOS
set_io hdmi_n[2] 79 -io_std SB_LVCMOS
set_io hdmi_n[1] 81 -io_std SB_LVCMOS
set_io hdmi_n[3] 136 -io_std SB_LVCMOS

set_io clk100 49

`default_nettype none // disable implicit definitions by Verilog
//-----------------------------------------------------------------
// minimalDVID_encoder.vhd : A quick and dirty DVI-D implementation
//
// Author: Mike Field <hamster@snap.net.nz>
//
// DVI-D uses TMDS as the 'on the wire' protocol, where each 8-bit
// value is mapped to one or two 10-bit symbols, depending on how
// many 1s or 0s have been sent. This makes it a DC balanced protocol,
// as a correctly implemented stream will have (almost) an equal
// number of 1s and 0s.
//
// Because of this implementation quite complex. By restricting the
// symbols to a subset of eight symbols, all of which having have
// five ones (and therefore five zeros) this complexity drops away
// leaving a simple implementation. Combined with a DDR register to
// send the symbols the complexity is kept very low.
//-----------------------------------------------------------------

module top(
clk100, hdmi_p, hdmi_n
);

input clk100;
output [3:0] hdmi_p;
output [3:0] hdmi_n;

// For holding the outward bound TMDS symbols in the slow and fast domain
reg [9:0] c0_symbol; reg [9:0] c0_high_speed;
reg [9:0] c1_symbol; reg [9:0] c1_high_speed;
reg [9:0] c2_symbol; reg [9:0] c2_high_speed;
reg [9:0] clk_high_speed;

reg [1:0] c2_output_bits;
reg [1:0] c1_output_bits;
reg [1:0] c0_output_bits;
reg [1:0] clk_output_bits;

wire clk_x5;
reg [2:0] latch_high_speed = 3'b100; // Controlling the transfers into the high speed domain

wire vsync, hsync;
wire [1:0] syncs; // To glue the HSYNC and VSYNC into the control character
assign syncs = {vsync, hsync};

// video structure constants
parameter hpixels = 800; // horizontal pixels per line
parameter vlines = 525; // vertical lines per frame
parameter hpulse = 96; // hsync pulse length
parameter vpulse = 2; // vsync pulse length
parameter hbp = 144; // end of horizontal back porch (96 + 48)
parameter hfp = 784; // beginning of horizontal front porch (800 - 16)
parameter vbp = 35; // end of vertical back porch (2 + 33)
parameter vfp = 515; // beginning of vertical front porch (525 - 10)

// registers for storing the horizontal & vertical counters
reg [9:0] vc;
reg [9:0] hc;
// generate sync pulses (active high)
assign vsync = (vc < vpulse);
assign hsync = (hc < hpulse);

always @(posedge clk_x5) begin
//-------------------------------------------------------------
// Now take the 10-bit words and take it into the high-speed
// clock domain once every five cycles.
//
// Then send out two bits every clock cycle using DDR output
// registers.
//-------------------------------------------------------------
c0_output_bits <= c0_high_speed[1:0];
c1_output_bits <= c1_high_speed[1:0];
c2_output_bits <= c2_high_speed[1:0];
clk_output_bits <= clk_high_speed[1:0];
if (latch_high_speed[2]) begin // pixel clock 25MHz
c0_high_speed <= c0_symbol;
c1_high_speed <= c1_symbol;
c2_high_speed <= c2_symbol;
clk_high_speed <= 10'b0000011111;
latch_high_speed <= 3'b000;
if (hc < hpixels)
hc <= hc + 1;
else
begin
hc <= 0;
if (vc < vlines)
vc <= vc + 1;
else
vc <= 0;
end
end
else begin
c0_high_speed <= {2'b00, c0_high_speed[9:2]};
c1_high_speed <= {2'b00, c1_high_speed[9:2]};
c2_high_speed <= {2'b00, c2_high_speed[9:2]};
clk_high_speed <= {2'b00, clk_high_speed[9:2]};
latch_high_speed <= latch_high_speed + 1'b1;
end
end

always @(*) // display 100% saturation colourbars
begin
// first check if we're within vertical active video range
if (vc >= vbp && vc < vfp)
begin
// now display different colours every 80 pixels
// while we're within the active horizontal range
// -----------------
// display white bar
if (hc >= hbp && hc < (hbp+80))
begin
c2_symbol = 10'b1011110000; // red
c1_symbol = 10'b1011110000; // green
c0_symbol = 10'b1011110000; // blue
end
// display yellow bar
else if (hc >= (hbp+80) && hc < (hbp+160))
begin
c2_symbol = 10'b1011110000; // red
c1_symbol = 10'b1011110000; // green
c0_symbol = 10'b0111110000; // blue
end
// display cyan bar
else if (hc >= (hbp+160) && hc < (hbp+240))
begin
c2_symbol = 10'b0111110000; // red
c1_symbol = 10'b1011110000; // green
c0_symbol = 10'b1011110000; // blue
end
// display green bar
else if (hc >= (hbp+240) && hc < (hbp+320))
begin
c2_symbol = 10'b0111110000; // red
c1_symbol = 10'b1011110000; // green
c0_symbol = 10'b0111110000; // blue
end
// display magenta bar
else if (hc >= (hbp+320) && hc < (hbp+400))
begin
c2_symbol = 10'b1011110000; // red
c1_symbol = 10'b0111110000; // green
c0_symbol = 10'b1011110000; // blue
end
// display red bar
else if (hc >= (hbp+400) && hc < (hbp+480))
begin
c2_symbol = 10'b1011110000; // red
c1_symbol = 10'b0111110000; // green
c0_symbol = 10'b0111110000; // blue
end
// display blue bar
else if (hc >= (hbp+480) && hc < (hbp+560))
begin
c2_symbol = 10'b0111110000; // red
c1_symbol = 10'b0111110000; // green
c0_symbol = 10'b1011110000; // blue
end
// display black bar
else if (hc >= (hbp+560) && hc < hfp)
begin
c2_symbol = 10'b0111110000; // red
c1_symbol = 10'b0111110000; // green
c0_symbol = 10'b0111110000; // blue
end
// we're outside active horizontal range
else
begin
c2_symbol = 10'b1101010100; // red
c1_symbol = 10'b1101010100; // green
//---------------------------------------------
// Channel 0 carries the blue pixels, and also
// includes the HSYNC and VSYNCs during
// the CTL (blanking) periods.
//---------------------------------------------
case (syncs)
2'b00 : c0_symbol = 10'b1101010100;
2'b01 : c0_symbol = 10'b0010101011;
2'b10 : c0_symbol = 10'b0101010100;
default : c0_symbol = 10'b1010101011;
endcase
end
end
// we're outside active vertical range
else
begin
c2_symbol = 10'b1101010100; // red
c1_symbol = 10'b1101010100; // green
//---------------------------------------------
// Channel 0 carries the blue pixels, and also
// includes the HSYNC and VSYNCs during
// the CTL (blanking) periods.
//---------------------------------------------
case (syncs)
2'b00 : c0_symbol = 10'b1101010100;
2'b01 : c0_symbol = 10'b0010101011;
2'b10 : c0_symbol = 10'b0101010100;
default : c0_symbol = 10'b1010101011;
endcase
end
end

// red N
defparam hdmin2.PIN_TYPE = 6'b010000;
defparam hdmin2.IO_STANDARD = "SB_LVCMOS";
SB_IO hdmin2 (
.PACKAGE_PIN (hdmi_n[2]),
.CLOCK_ENABLE (1'b1),
.OUTPUT_CLK (clk_x5),
.OUTPUT_ENABLE (1'b1),
.D_OUT_0 (~c2_output_bits[1]),
.D_OUT_1 (~c2_output_bits[0])
);

// red P
defparam hdmip2.PIN_TYPE = 6'b010000;
defparam hdmip2.IO_STANDARD = "SB_LVCMOS";
SB_IO hdmip2 (
.PACKAGE_PIN (hdmi_p[2]),
.CLOCK_ENABLE (1'b1),
.OUTPUT_CLK (clk_x5),
.OUTPUT_ENABLE (1'b1),
.D_OUT_0 (c2_output_bits[1]),
.D_OUT_1 (c2_output_bits[0])
);

// green N
defparam hdmin1.PIN_TYPE = 6'b010000;
defparam hdmin1.IO_STANDARD = "SB_LVCMOS";
SB_IO hdmin1 (
.PACKAGE_PIN (hdmi_n[1]),
.CLOCK_ENABLE (1'b1),
.OUTPUT_CLK (clk_x5),
.OUTPUT_ENABLE (1'b1),
.D_OUT_0 (~c1_output_bits[1]),
.D_OUT_1 (~c1_output_bits[0])
);

// green P
defparam hdmip1.PIN_TYPE = 6'b010000;
defparam hdmip1.IO_STANDARD = "SB_LVCMOS";
SB_IO hdmip1 (
.PACKAGE_PIN (hdmi_p[1]),
.CLOCK_ENABLE (1'b1),
.OUTPUT_CLK (clk_x5),
.OUTPUT_ENABLE (1'b1),
.D_OUT_0 (c1_output_bits[1]),
.D_OUT_1 (c1_output_bits[0])
);


// blue N
defparam hdmin0.PIN_TYPE = 6'b010000;
defparam hdmin0.IO_STANDARD = "SB_LVCMOS";
SB_IO hdmin0 (
.PACKAGE_PIN (hdmi_n[0]),
.CLOCK_ENABLE (1'b1),
.OUTPUT_CLK (clk_x5),
.OUTPUT_ENABLE (1'b1),
.D_OUT_0 (~c0_output_bits[1]),
.D_OUT_1 (~c0_output_bits[0])
);

// blue P
defparam hdmip0.PIN_TYPE = 6'b010000;
defparam hdmip0.IO_STANDARD = "SB_LVCMOS";
SB_IO hdmip0 (
.PACKAGE_PIN (hdmi_p[0]),
.CLOCK_ENABLE (1'b1),
.OUTPUT_CLK (clk_x5),
.OUTPUT_ENABLE (1'b1),
.D_OUT_0 (c0_output_bits[1]),
.D_OUT_1 (c0_output_bits[0])
);

// clock N
defparam hdmin3.PIN_TYPE = 6'b010000;
defparam hdmin3.IO_STANDARD = "SB_LVCMOS";
SB_IO hdmin3 (
.PACKAGE_PIN (hdmi_n[3]),
.CLOCK_ENABLE (1'b1),
.OUTPUT_CLK (clk_x5),
.OUTPUT_ENABLE (1'b1),
.D_OUT_0 (~clk_output_bits[1]),
.D_OUT_1 (~clk_output_bits[0])
);


// clock P
defparam hdmip3.PIN_TYPE = 6'b010000;
defparam hdmip3.IO_STANDARD = "SB_LVCMOS";
SB_IO hdmip3 (
.PACKAGE_PIN (hdmi_p[3]),
.CLOCK_ENABLE (1'b1),
.OUTPUT_CLK (clk_x5),
.OUTPUT_ENABLE (1'b1),
.D_OUT_0 (clk_output_bits[1]),
.D_OUT_1 (clk_output_bits[0])
);
// D_OUT_0 and D_OUT_1 swapped?
// https://github.com/YosysHQ/yosys/issues/330


SB_PLL40_PAD #(
.FEEDBACK_PATH ("SIMPLE"),
.DIVR (4'b0000),
.DIVF (7'b0001001),
.DIVQ (3'b011),
.FILTER_RANGE (3'b101)
) uut (
.RESETB (1'b1),
.BYPASS (1'b0),
.PACKAGEPIN (clk100),
.PLLOUTGLOBAL (clk_x5) // DVI clock 125MHz
);

endmodule

git clone https://github.com/flashrom/flashrom.git

cd flashrommake

sudo CONFIG_ENABLE_LIBPCI_PROGRAMMERS=no CONFIG_ENABLE_LIBUSB0_PROGRAMMERS=no CONFIG_ENABLE_LIBUSB1_PROGRAMMERS=no install

echo 24 > /sys/class/gpio/export

echo out > /sys/class/gpio/gpio24/direction

flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=20000 -r dump

flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=20000 -w dump

tr '\0' '\377' < /dev/zero | dd bs=2M count=1 of=image
dd if=my_bitstream conv=notrunc of=image

echo 24 > /sys/class/gpio/export

echo out > /sys/class/gpio/gpio24/direction

flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=20000 -w FPGA.bin

echo in > /sys/class/gpio/gpio24/direction

// A nice Azure blue for example :
c2_symbol = 10'b1111010000; // red
c1_symbol = 10'b1011110000; // green
c0_symbol = 10'b1011110000; // blue

c2_symbol = 10'b1111111111; // red
c1_symbol = 10'b1111111111; // green
c0_symbol = 10'b1111111111; // blue

c2_symbol = 10'b0000000000; // red
c1_symbol = 10'b0000000000; // green
c0_symbol = 10'b0000000000; // blue

I have an idea for a next “chapter” in my project : prepared computers or assemblages.

Each computer would be a hodge-podge of different tech from different eras, but would each include some kind of I/O, memory, ALU, and display, cooling. I could return to the e-waste side of things, but still make circuits to control them.

I could use a corps exquis method to combine different types of screens/displays :

• mini CRT
• LCD
• projector
• printer
• e-ink
• galvo lasers

Types of memory :

• floppy
• SRAM
• DDR
• CD
• Tape

ALU :

• FPGA
• microcontroller
• raspberry pi
• mechanical

I/O :

• mouse
• keyboard
• trackball
• touchpad
• speakers
• internet

Cooling

• Peltier
• Fan
• Radiator

The actual functions of the computers would be unclear, they would generate mysterious images and sequences and react to the interface. They would allow me to very clearly be in the practice of making art.

They would highlight what I’ve come to find interesting about the world of computers, the hand-madeness and social dimension of the objects. Each would be unique, idiosyncratic, and I would no longer be in the situation of working with screens and not knowing what exactly the “object” is. The object here would be clear, it would be the computer assemblage. I could revisit my obsession with miniatureness, and oddity in these hybrid “monsters”. They would also require lots of technical challenges to make work, and would not produce waste like the mass production of circuit boards does when making a kit.

This is building on Vivien’s idea to be inspired by full computer builds to emphasize materiality :

It would be really cool to make everything from e-waste, but also to keep the miniature dimensions. It looks like phone screens from Nokia can be controlled by Arduino, but that others are undocumented and hard to control without finding a datasheet :

Some ressources for controlling a TFT display directly with Arduino :

https://community.element14.com/members-area/personalblogs/b/blog/posts/screen-success-hack-like-heck-build-update

Looks like it is doable with a raspberry pi and therefore doable with an FPGA.

None of these will be possible if I don’t have an autonomous board though – one that produces it’s own videos with data (instead of relying on video from a computer or rapsberry pi). So I will have to make this work first, and why not try to have this done for the expo next month in Germany ?

******

This Autonomous board could play videos from memory and display it all on the same board, without any wires !

I am now seeing this as a two board construction. The keyboard is too dense to pack any electronics into really, so it is better just as an interface with a ribbon cable going to the board behind the screen which has the FPGA and microcontroller. The bottom could be in aluminium which would make it stable and could have tabs which bend on the edges. This would provide a solid mounting place for the micrometer knob and the laptop hinge. It would also give a different look to the board as it would be all metal, combining with the micrometer, the screen and the screen hinge to make an all metal looking assemblage.

Not yet sure how to convert the linear motion of the micrometer knob, and I feel that the screen + board might look and be a little top heavy / too thick for the effect.

Check out these beautiful machines from Love Hulten : https://www.lovehulten.com/ Thanks Martin De bie for the ref !

Now I’m thinking it should be flat in fact :

Looking in to TFT LCDs, here’s what I’m finding :

• 40 pins seems to be a kind of standard
• There seems to be at least two modes : ‘RGB’ mode and SPI mode.
• rectangular screens with 800×480 in 4.3″, 5″ or 7″ seems to be standard
• TFTs seem to come with a driver chip like the ILI9341 or the ST7701S
• Some seem to require being initialized by SPI

*****

Kristy has helped me select a nice sized screen, 2.8″ seems to be cute but not trinket-like. Adafruit’s screen sells on Mouser : https://www.adafruit.com/product/1774

It appears to have a simple 8 bit parallel mode by default with a straight-forward timing diagram :

And here’s another explanation of the same thing showing two different options :

The datasheet is detailed and I have Adafruit code to base things on as well.

****

The screen also appears to also have a “raw” Parallel RGB Interface mode which seems to involve the HSYNC, VSYNC, DOTCLOCK, DE, while sending color data to the D pins…..but it looks like first bits (RCM, RIM, and DPI) must be set from the SPI mode ? Also, it looks like you have to calculate yourself the timings of the screen based on the clock and screen dimensions (and also set these bits (DIV, RTN, etc.) ? But it looks super simple afterward :

*************

PROJECT UPDATE :

This project seems to be unlucky :

• My Mouser order was stolen from inside my building or was never actually delivered.
• The idea of having doublesided PCB + aluminum went out the window when I saw the cost (approx. 10x a normal PCB)
• The replacement screen I ordered from Amazon has only 20 connections (instead of 50) and only allows SPI, which is very difficult for the FPGA to do and so would require a microchip + FPGA teamwork which seems technically a real headache.
• Currently the HX4K is not starting up, despite having both PLLs connected now. I’m not sure what I’m missing but it is different enough from the HX1K to merit more research before using I guess.

On the other hand I have been preparing for my ESDAC creative coding class and enjoying learning about the different kinds of P5JS codes that exist. I made an image to show the typologies I found so far :

I should also have a class on Glitching !!! And on WEBGL Shader, check out this awesome book : https://thebookofshaders.com/03/

Moiré

Field

Random walk

Spirograph

Cavegen

Radial

Hyper-realistic face generation

**********

Trying to put together an analysis of the kind of hardware effects I have been producing so far :

Here is a slide trying to show the process of designing a board :

And some sketches of circuits I’ve made over the course of the project :

****

Older board I never photographed :

****

I finally have access to opencores.org ! Some things of interest so far :

• Math – https://opencores.org/projects/verilog_fixed_point_math_library
• Noise and PRNG  – https://opencores.org/projects/gng
• CORDIC core (for trig functions) – https://opencores.org/projects/verilog_cordic_core
• ATTINY core – https://opencores.org/projects/attiny_atmega_xmega_core

There is plenty more, like H.264 and JPEG decoding, SoC, sorting algorithms, DDR controllers, Real-time clocks, PCI bus controllers, DSP Filters, SD card controllers, SPI/UART/USB/I2C etc interfaces, etc.

****

Some aesthetic references I was reminded of this week :

• The fractal, “trippy”, spaceship-like camera movements, and kaleidescopic winamp visuals : https://www.youtube.com/watch?v=RBkhUg1oVIE

• The black and white retro dithering from Return Of The Obra Dinn https://www.youtube.com/watch?v=k2y5qH2Jn14
• 

*************

Post Darmstadt workshop thoughts :

• CNC building workshops are hard. In the Fab Academy it takes an entire team two weeks. My two attempts, a while back at CMU and in Germany this week were too ambitious. If I want to have everyone leave with a working machine I need to do a lot of prep before hand. This weekend I could have 3D printed parts before hand that clipped together in the spirit of my linear actuators for the Fab Ac (https://www.marrs.io/medium-sized-cnc-foam-cutter-with-leon-reboul/). Alternatively I could have bought a cheap drawing kit from Aliexpress for around 100 euros if I had gotten myself organized early enough. I think threaded rods may also be a better solution than belt drives which require more skill to design with. The linear rails were cool but they required special low-profile screws so the students struggled a bit with this. It also seems to be the case that servos can simply replace all the challenges of stepper motors requiring drivers for everyone but experts. Essentially : Don’t overthink it, do the most obvious tech thing that is the shortest path for beginners. This will be my strategy for the Beaux Arts workshop coming up where I’ll focus on servos only.
• I should probably keep in mind the challenge of the workshop. The higher the challenge for the participants, the more work I need to do to prepare everything. More plug and play = less challenge.
• Learning to be a free lancer will take time but I need to consider myself as a professional, not doing things on a shoestring budget and exhausting myself. As I move around and workshop in different places, I need to keep in mind my audience – engineering students are different from artists, designers, enthusiasts and kids.
• It might be cool to learn to make video PDFs for future presentations when talking about video synthesis. Also maybe live coding with toy shader / P5JS to illustrate things ?
• For the expo, I was happy to have a plug and play FPGA solution that just generated images. The boards I have made that record video all need heavy intervention on the part of the player and are not intuitive at all. I am still hoping to find a way to order the remaining parts from Mouser soon so I can test SD card reading and FPGA screen displaying.
• For my talk, I still don’t have a way of directly connecting my earlier projects with the new video synth project.

Next steps :

I am feeling positively about just following my interests, and not necessarily knowing where I am going with this project. I want to :

• make abstract generating form code with FPGA using the new trig functions, multiplication and division from opencores !
• experiment with more filters using the FPGA.
• move beyond my current aesthetic, which will require making the recorded image not jump around. I should be able to do this pretty easily when the FPGA is sending the sync signals.

*************

Post BA workshop thoughts :

• The students this time were really into following a more formal series of prepared slides with exercises, and seemed less interested in building their own drawing machines. The Arduino exercises were well received, as well as the glitch exercise, and also the soldering workshop. I like that they bring their own projects and integrate them.
• I tried to be extra professional this time, staying late with students to continue helping them, being extra careful to put everything back in its proper place, and generally being as uncompromising as possible in the quality I’m trying to bring to the workshop.
• My little polyphonic synth, portable speaker, and VGA arduino board were a good thing to bring. I should have something interactive that puts images on the screen I think and a lamp to show off the solar sunflower too.
• I had too many projects to manage in parallel at one point and was rushing about everywhere. Not sure what the solution is there, there were around 8/9 people for the first two days.
• We need some basic boards like mic amp, speaker amp, easy stepper motor drivers, relay boards, etc. that are useful at the BD.
• Vincent was suggesting that we think of ways of creating a virtual expo space for digital works somehow in relation to his radio station at the school which is appreciated.

*************

Post website being down, looking at previous pages now and having some perspective thoughts :

• pure p5js coding I find far less exciting than hardware visual effects, it’s all too immediate and mediated. It’s not raw and unstable like analogue. I think I’m more convinced that the painful process of doing simple things the hardest way possible is actually productive creatively for the friction it affords.
• Putting a series of bitmaps on an SD card (possibly with a custom FFMPEG running on raspberry pi) and then onto the screen would be cool. The idea for a custom FFMPEG comes from this tutorial http://dranger.com/ffmpeg/tutorial01.html which I found here https://github.com/codecrafters-io/build-your-own-x which I in turn found on reddit FREE MEDIA HECK YES 
• I need to get the sync working to test some other (less jarring) visual experiences.
• The Real Time Corrupter methods (piping, etc.) are brilliant and I have to copy them to experiment with FPGA memory filters. Beyond the RTC it would be very cool to experiment with DCT compression filter spectra.
• I don’t think I need to look under each hole and check under each rock. Getting one type of memory working, and one video protocol, is good enough and I don’t need to suffer with DDR and HDMI in this way of working I’m assuming currently.
• For marketing video synths, there is the website php like Marc did (https://muca.cc/fr) or the instagram/facebook marketplace option. Alternatively there are services that host the payment side of things like gumroad, prestashop, and wordpress https://wordpress.com/fr/ecommerce/
• I’m doing NO SCHOOL this summer !! Planning on getting a simple FPGA v synth programmable with Arduino / RPI in python and made on an aluminum-backed board (with SMD VGA).

*************

Learned about live coding with hydra :

I will be VJing this month, we’ll see what that experience is like. Perhaps it will help me design boards that VJs could use. Here’s what I learned :

• The stress of doing a live performance when everything isn’t set up and rehearsed many times before hand is high. One would need to have a bunch of backups, and a very rehearsed performance to lower stress.
• Having a small lamp is helpful to see what connections and knobs you are messing with
• One question is how to react to music, does a beat equal a varying of a parameter ? How to react to song changes ?
• How should “effects” be introduced ? I defaulted towards starting simple and then going towards the more complex effects
• Clearly having performance grade equipment means everything is super robust, easy to use, etc. This makes me think that it would make sense to make a really reliable simple filter, for instance. This also connects with a larger issue for me : I want to do things differently but there are often good reasons why things are done a particular way…
• Sending my crazy VGA to a machine that digitizes it and sends it on as HDMI is probably safer than directly sending things to the projector…

I want to use an older media device (cassette tape, floppy, mini-VHS?) in my next board. I realized that if my practice is about “doing things the hard way”, that should be visually communicated in the design (no one understands if the electronics are done the hard way or not…). This would also signal that I am not trying to make cutting edge new things but that my interests are elsewhere.

Here is a first look at some video synth companies and their designs :

Trying again with the floppy drive :

Check out this video extracting motion from video by just inverting and sliding videos sideways :

****************

I finally bought preparedinstruments.com ! Here are some potential designs for the page :

Making a simple FPGA video synth for PEW 2023 at Villette Makerz. It takes audio in and generates patterns based on the voltage threshold and the 9 keys being pressed.

The code is here : https://github.com/merlinmarrs/iCE40HX-verilog-video-patterns

This time the top interface side has only buttons and no electronics. I have a simplified VGA out and HDMI with the correct LVDS resistor setup this time. I am relying on raspberry pi or arduino for programming.

Trying a grid ground pour on the Stop layer :

Here’s the final soldered version :

Nicer photos :

Found a site called OpenCores (https://opencores.org) that has free FPGA IP like math libraries.

Here are some tests with cool looking patterns :

Because dividing, trig functions, etc. aren’t supported by default, the most promising is the bitwise boolean logic operating on the entire vector :

wire[11:0] bit_or;
assign bit_or = h_count[11:0] | v_count[11:0];

[...]

if (bit_or[5] == 1 | bit_or[3] == 0) begin

wire[11:0] bit_xor;
assign bit_xor = h_count[11:0]^v_count[11:0];

[...]

if (bit_xor[2] == 1 | bit_xor[4] == 1) begin

wire[11:0] bit_and;
assign bit_and = h_count[11:0]&v_count[11:0];

...

if (bit_and[6] == 1 | bit_xor[7] == 1) begin

I could imagine having the keys vary which logic operations are in play and having the music threshold change the color of the pixels for instance.

***

This site has a module for a quasi random number generator : https://simplefpga.blogspot.com/2013/02/random-number-generator-in-verilog-fpga.html

This site has some good Processing examples : http://www.generative-gestaltung.de/2/

***

If I do this workshop again I’d like to design it to be made on aluminum as, it is at least in principle, recyclable.

PCBWay’s diagram of a double layer board (https://www.pcbway.fr/pcb_prototype/General_introduction_of_Aluminum_PCB.html) :

***

Simplest imaginable keypad switch (and audio in post comparator) test works :

module top (
input hwclk,
output led1,
input keypad_c1
);

assign led1=keypad_c1;

endmodule

`default_nettype none

module LFSR (
input clock,
input reset,
output [12:0] rnd
);

wire feedback;
reg [12:0] random, random_done;
reg [3:0] count; //to keep track of the shifts

assign feedback = random[12] ^ random[3] ^ random[2] ^ random[0];
assign rnd = random_done;
always @ (posedge clock)
begin
if (reset)
begin
random <= 13'hF; //An LFSR cannot have an all 0 state, thus reset to FF
count <= 0;
end

else
begin
if (count == 13)
begin
count <= 0;
random_done <= random; //assign the random number to output after 13 shifts
end

else
begin
random <= {random[11:0], feedback}; //shift left the xor'd every posedge clock
count <= count + 1;
end
end
end
endmodule

wire [12:0] random_number;

[...]

LFSR random_s(
.clock(clk_in),
.reset(reset),
.rnd(random_number)
);

`default_nettype none
module tempo(
input wire clk,
output reg half_sec_pulse
);

reg[25:0] div_cntr1;
reg[25:0] div_cntr2;
always@(posedge clk)
begin
div_cntr1 <= div_cntr1 + 1;
if (div_cntr1 == 0)
if (div_cntr2 == 0)
begin
div_cntr2 <= 0;
half_sec_pulse <= ~half_sec_pulse;
end

else
div_cntr2 <= div_cntr2 + 1;
else
half_sec_pulse <= half_sec_pulse;
end

endmodule

`default_nettype none

module vga_sync_test(

input wire clk_in,
input wire reset,
input wire key[8:0],
input wire adc_in,
output reg led_red,
output reg led_green,

//VGA OUT

output reg [3:0] r_out,
output reg [3:0] b_out,
output reg [3:0] g_out,
output wire h_sync,
output wire v_sync

);

wire half_sec;
wire [12:0] random_number_0;
wire [12:0] random_number_1;
wire [12:0] random_number_2;
wire [12:0] random_number_3;
wire [12:0] random_number_4;
wire [12:0] random_number_5;
wire [12:0] random_number_6;
wire [12:0] random_number_7;
wire [12:0] random_number_8;
wire [12:0] random_number_9;
wire [7:0] sine_wave;
wire display_en;
wire [11:0] h_count;
wire [11:0] v_count;

localparam h_pixel_max = 1280;
localparam v_pixel_max = 960;
localparam h_pixel_half = 640;
localparam v_pixel_half = 480;
localparam h_pixel_25 = 320;
localparam v_pixel_25 = 240;
localparam h_pixel_75 = 960;
localparam v_pixel_75 = 700;

//VGA COLOR OUT

always @(posedge clk_in) begin

if (display_en) begin

if ( key[0] == 0 &&

h_count < h_pixel_25 + random_number_1[4:0] && v_count < v_pixel_25 + random_number_7[8:5] &&
h_count > h_pixel_25 - random_number_2[4:0] && v_count > v_pixel_25 - random_number_2[8:5]

) begin

r_out <= random_number_1[3:0];
g_out <= random_number_5[3:0];
b_out <= random_number_9[6:4];

led_green <= 1;

end

else if ( key[1] == 0 &&

h_count < h_pixel_half + random_number_7[5:0] && v_count < v_pixel_half + random_number_7[10:5] &&
h_count > h_pixel_25 - random_number_6[5:0] && v_count > v_pixel_25 - random_number_6[10:5]

) begin

r_out <= random_number_3[7:5];
g_out <= random_number_3[3:0];
b_out <= random_number_6[6:4];

led_green <= 1;

end

else if ( key[2] == 0 &&

h_count < h_pixel_25 + random_number_8[6:0] && v_count < v_pixel_25 + random_number_8[12:6] &&
h_count > h_pixel_half - random_number_9[6:0] && v_count > v_pixel_half - random_number_9[11:5]

) begin

r_out <= random_number_4[7:5];
g_out <= random_number_5[3:0];
b_out <= random_number_7[6:4];
led_green <= 1;

end

else if ( key[3] == 0 &&

h_count < h_pixel_half + random_number_0[7:0] && v_count < v_pixel_half + random_number_0[7:0] &&
h_count > h_pixel_half - random_number_3[7:0] && v_count > v_pixel_half - random_number_3[11:4]

) begin

r_out <= random_number_8[7:5];
g_out <= random_number_8[3:0];
b_out <= random_number_8[6:4];
led_green <= 1;

end

else if ( key[4] == 0 &&

h_count < h_pixel_75 + random_number_2[8:0] && v_count < v_pixel_half + random_number_2[11:3] &&
h_count > h_pixel_75 - random_number_4[8:0] && v_count > v_pixel_half - random_number_4[11:3]

) begin

r_out <= random_number_7[7:5];
g_out <= random_number_7[3:0];
b_out <= random_number_7[6:4];

led_green <= 1;

end

else if ( key[5] == 0 &&
h_count < h_pixel_half + random_number_3[9:0] && v_count < v_pixel_75 + random_number_3[11:2] &&
h_count > h_pixel_half - random_number_8[9:0] && v_count > v_pixel_75 - random_number_8[11:2]

) begin

r_out <= random_number_5[7:5];
g_out <= random_number_5[3:0];
b_out <= random_number_5[6:4];
led_green <= 1;

end

else if ( key[6] == 0 &&

h_count < h_pixel_75 + random_number_4[10:0] && v_count < v_pixel_75 + random_number_4[11:1] &&
h_count > h_pixel_75 - random_number_6[10:0] && v_count > v_pixel_75 - random_number_6[11:1]

) begin
r_out <= random_number_4[7:5];
g_out <= random_number_4[3:0];
b_out <= random_number_4[6:4];
led_green <= 1;
end
else begin
r_out <= random_number_2[3:0];
g_out <= random_number_3[6:4];
b_out <= random_number_4[3:0];
led_green <= 0;
end
end
else begin
r_out <= 4'b0000;
g_out <= 4'b0000;
b_out <= 4'b0000;
led_green <= 0;
end
end

vga_sync vga_s(

.clk_in(clk_in),
.reset(reset),
.h_sync(h_sync),
.v_sync(v_sync),
.h_count(h_count),
.v_count(v_count),

.display_en(display_en) // '1' => pixel region

);

LFSR random_s(

.clock(clk_in),
.reset(reset),
.half_sec_pulse(half_sec),
.rnd_0(random_number_0),
.rnd_1(random_number_1),
.rnd_2(random_number_2),
.rnd_3(random_number_3),
.rnd_4(random_number_4),
.rnd_5(random_number_5),
.rnd_6(random_number_6),
.rnd_7(random_number_7),
.rnd_8(random_number_8),
.rnd_9(random_number_9)
);

sine_wave_gen sine_wave_s(
.clk(clk_in),
.data_out(sine_wave)
);

tempo tempo_s(
.clk(clk_in),
.half_sec_pulse(half_sec)
);

endmodule

set_io v_sync 97
set_io h_sync 76
set_io clk_in 49
set_io reset 66

set_io r_out[0] 91
set_io r_out[1] 95
set_io r_out[2] 96

set_io g_out[0] 75
set_io g_out[1] 74
set_io g_out[2] 73

set_io b_out[0] 87
set_io b_out[1] 88
set_io b_out[2] 90

set_io key[0] 37
set_io key[1] 38
set_io key[2] 39
set_io key[3] 41
set_io key[4] 42
set_io key[5] 43
set_io key[6] 44
set_io key[7] 45
set_io key[8] 47
set_io led_red 23
set_io led_green 24
set_io adc_in 56

/*
 * Created by ArduinoGetStarted.com
 *
 * This example code is in the public domain
 *
 * Tutorial page: https://arduinogetstarted.com/reference/library/arduino-file.readbytes
 */


#include <SD.h>


#define PIN_SPI_CS 4


File file;
char buf[200];


void setup() {
  Serial.begin(9600);
  DDRD = B11111111;


  if (!SD.begin(PIN_SPI_CS)) {
    Serial.println(F("SD CARD FAILED, OR NOT PRESENT!"));
    while (1); // don't do anything more:
  }


  // open file for reading
  file = SD.open("albers.hex", FILE_READ);
  if (file) {
    int avail_len = file.available();
    int read_len = file.readBytes(buf, avail_len); // read all to buffer to buffer


    Serial.print("Length:");
    Serial.println(read_len);
    Serial.println("Content:");


              for (int i=0; i<200; i++) {
   
    Serial.print(byte(buf[i]));
    PORTD = byte(buf[i]);
          }
   


    file.close();
  } else {
    Serial.print(F("SD Card: error on opening file"));
  }
}


void loop() {
}

`default_nettype none

module vga_sync_test(

input wire clk_in,
input wire reset,

input wire rec, // Direction of io, 1 = set output, 0 = read input

//RASPBERRY PI
input wire [3:0] r_in,
input wire [3:0] b_in,
input wire [3:0] g_in,

//VGA OUT
output reg [3:0] r_out,
output reg [3:0] b_out,
output reg [3:0] g_out,

output wire h_sync,
output wire v_sync,

//SRAM

output reg [20:0] addr,
inout wire [7:0] io, // inout must be type wire

output wire cs_1,
output wire cs_0,
output reg we_0

);


wire half_sec;

wire [12:0] random_number_0;
wire [12:0] random_number_1;
wire [12:0] random_number_2;
wire [12:0] random_number_3;
wire [12:0] random_number_4;
wire [12:0] random_number_5;
wire [12:0] random_number_6;
wire [12:0] random_number_7;
wire [12:0] random_number_8;
wire [12:0] random_number_9;
wire [7:0] sine_wave;

wire [7:0] data_in;
wire [7:0] data_out;

reg toggle;

reg [7:0] a, b;

assign io = rec ? a : 8'bzzzzzzzz;

assign data_out = b;

assign data_in[1:0] = r_in[3:2];
assign data_in[3:2] = b_in[3:2];
assign data_in[5:4] = g_in[3:2];
assign data_in[7:6] = 2'b00;

wire display_en;
wire [11:0] h_count;
wire [11:0] v_count;

localparam h_pixel_max = 1280;
localparam v_pixel_max = 960;
localparam h_pixel_half = 640;
localparam v_pixel_half = 480;


reg [1:0] count2; //to keep track of the shifts

wire [11:0] bit_or;
assign bit_or = h_count[11:0]|v_count[11:0];

wire [11:0] bit_xor;
assign bit_xor = h_count[11:0]^v_count[11:0];

wire [11:0] bit_and;
assign bit_and = h_count[11:0]&v_count[11:0];

wire [11:0] bit_nand;
assign bit_nand = h_count[11:0]& ~v_count[11:0];

wire [11:0] bit_xnor;
assign bit_xnor = h_count[11:0]^ ~v_count[11:0];

reg [11:0] out_bit ;


// CS: low to select, high to deselect

assign cs_0 = toggle ? 1 : 0;
assign cs_1 = toggle ? 0 : 1;

//SRAM address counter

always @(posedge clk_in) begin

if (addr == 0) begin
toggle <= toggle+1;
end

if (reset) begin
addr <= 0;
end else begin
addr <= addr+1;

end
end


//REC control

always @(posedge clk_in) begin

b <= io;
a <= data_in;

if (rec) begin
we_0 <= addr[0]; //not sure why it isn't the inverse of addr[0] but that doesn't make the inverse on 'scope
end
else begin
we_0 <= 1;
end
end

//VGA COLOR OUT

always @(posedge clk_in) begin

case(count2)
2'b00: out_bit = bit_or;
2'b01: out_bit = bit_xor;
2'b10: out_bit = bit_and;
2'b11: out_bit = bit_nand;

default: out_bit = bit_xnor;
endcase
count2 <= count2 + 1;
end

//VGA COLOR OUT

always @(posedge clk_in) begin
if (display_en) begin

if (out_bit[random_number_2[3:0]] == 1 | out_bit[random_number_6[3:0]] == 0) begin

r_out <= random_number_2[3:0];
g_out <= random_number_3[3:0];
b_out <= random_number_4[3:0];

end

else begin

r_out[3:2] <= data_out[1:0];
r_out[1:0] <= data_out[1:0];
g_out[3:2] <= data_out[3:2];
g_out[1:0] <= data_out[3:2];
b_out[3:2] <= data_out[5:4];
b_out[1:0] <= data_out[5:4];

end

end else begin

r_out <= 4'b0000;
g_out <= 4'b0000;
b_out <= 4'b0000;

end
end

vga_sync vga_s(
.clk_in(clk_in),
.reset(reset),
.h_sync(h_sync),
.v_sync(v_sync),
.h_count(h_count),
.v_count(v_count),
.display_en(display_en) // '1' => pixel region
);

LFSR random_s(
.clock(clk_in),
.reset(reset),
.half_sec_pulse(half_sec),
.rnd_0(random_number_0),
.rnd_1(random_number_1),
.rnd_2(random_number_2),
.rnd_3(random_number_3),
.rnd_4(random_number_4),
.rnd_5(random_number_5),
.rnd_6(random_number_6),
.rnd_7(random_number_7),
.rnd_8(random_number_8),
.rnd_9(random_number_9)
);

sine_wave_gen sine_wave_s(
.clk(clk_in),
.data_out(sine_wave)
);

tempo tempo_s(
.clk(clk_in),
.half_sec_pulse(half_sec)
);

endmodule

FPGA SRAM board

Shadertoy is the future of this project, so what am I doing ? This new board is a reprogrammable FPGA 2D pixel shader (aka fragment shader) which can control the color of pixels and know only of the coordinate of the pixel being drawn. Pixel shaders can also sample the values of nearby pixels. As a result, they can do 2D post-processing (https://en.wikipedia.org/wiki/Video_post-processing) or filtering for a video streams. Why do this on an FPGA rather than in-brower ? You are super low level, and you have constraints based on the number of LUTs, it has a live-playable interface. In any case, I think this is my last board for a while, unless I can make an AI board somehow.

On the other hand, I’m not sure how profound it is to make photoshop like filters. (You can test a 5×5 grid if you go under Filters>Custom in PS). They are all kind of superficial…

I am starting to realize that I spend loads of time debugging soldering errors (yes, I get the learning that comes with that but still). If I made boards and had them assembled elsewhere I would not have this issue. Should I also, in the same spirit, just jump ahead to what everyone else is doing, with the thinking that they are not wasting time on problems that have already been solved and are exploring an interesting space.

I also spend a lot of time designing and building boards, interfaces, and less time programming them: the SCARA robot arm that I didn’t even plug in, the covid temperature interface board, the drone, and the MIT version of the mini swarm robot. On the other side are the projects I’ve perhaps spent too must time making and incrementally remaking perhaps : 3105 power harvester + radio transciever, the Ben Eater style memory. A nice balance was perhaps the solar sunflower protytpes which were experiments with form and function.

*EDIT* I am now thinking that I must work on things that would be of interest to other people, like Machine Learning for instance. I must be humble, just because something is interesting to me doesn’t mean anyone else cares ! Turns our that FPGAs consume a lot less current than GPUs so they are not bad for implementing ML once the training is done. Here is a info about ML with FPGAs :

• https://www.youtube.com/@marcowinzker3682
• https://www.mdpi.com/2076-3417/12/1/89
• https://github.com/verimake-team/MLonFPGA
• https://qengineering.eu/deep-learning-with-fpga-aka-bnn.html
• https://qengineering.eu/embedded-vision.html#FPGA_stitching

Great post about the marble machine project : https://www.reddit.com/r/MarbleMachineX/comments/pzh5kw/an_open_letter_to_martin_on_the_state_of_the/

• The machine is not about reliability and precision, it is about imperfection and the journey
• It’s an art project, it is a project for the project’s sake and the documentation.
• The project shouldn’t run like a start-up, and we are not the sum of what we produce for capitalism
• Not specializing in one thing is what makes this project cool.

ERRATA :

• I think the 590 is not clock dividing as expected…Is it not 3.3V compatible ? I think so, even though unclear on Mouser website.
• Currently only 2 bits of each raspberry pi color input are appearing despite having selected dpi24 in the rpi config file.
• The fine pots are the wrong footprint for the pots I have.
• I could have used DEN (display enable) from the raspi.
• sometimes the rpi starts up and then restarts after playing only a few seconds of video…not sure why.

To change the PLL, there is a tool in IceCube2 under Tool>Configure>Configure PLL Module

Here is the user guide explaining how to use it : https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/IK2/FPGA-TN-02052-1-4-iCE40-sysCLOCK-PLL-Design-User-Guide.ashx?document_id=47778

I want the following options :

• General Purpose I/O Pad or Core Logic
• Using a feedback path internal to the PLL
• Input Frequency (MHz) : 100
• Output Frequency (MHz) : 25
  

Here is the new PCF file :

set_io v_sync 87
set_io h_sync 88
set_io clk_in 64
set_io reset 66
set_io r0 81
set_io r1 80
set_io r2 79
set_io g0 94
set_io g1 93
set_io g2 91
set_io b0 76
set_io b1 75
set_io b2 74
set_io led 45
set_io locked_led 37

I made a pcf to go with this test code :

set_io R7IN 107
set_io R6IN 106
set_io R5IN 105
set_io R4IN 104
set_io G7IN 97
set_io G6IN 96
set_io G5IN 95
set_io G4IN 112
set_io B7IN 102
set_io B6IN 101
set_io B5IN 99
set_io B4IN 98
set_io R7OUT 81
set_io R6OUT 80
set_io R5OUT 79
set_io R4OUT 78
set_io G7OUT 94
set_io G6OUT 93
set_io G5OUT 91
set_io G4OUT 90
set_io B7OUT 76
set_io B6OUT 75
set_io B5OUT 74
set_io B4OUT 73

set_io v_sync 87
set_io h_sync 88
set_io clk_in 64
set_io reset 66
set_io r0 81
set_io r1 80
set_io r2 79
set_io g0 94
set_io g1 93
set_io g2 91
set_io b0 76
set_io b1 75
set_io b2 74

set_io io0 1
set_io io1 2
set_io io2 3
set_io io3 4
set_io io4 122
set_io io5 121
set_io io6 120
set_io io7 119

set_io a0 138
set_io a1 139
set_io a2 141
set_io a3 142
set_io a4 143
set_io a5 8
set_io a6 9
set_io a7 10
set_io a8 11
set_io a9 12
set_io a10 136
set_io a11 135
set_io a12 134
set_io a13 129
set_io a14 128
set_io a15 117
set_io a16 116
set_io a17 115
set_io a18 114
set_io a19 137
set_io a20 113

set_io cs1 71
set_io we0 7

Here are some images of what a new device could look like !

What about an FPGA chip holder ? And a snazzy pivotable SD card holder ? Using meanders this time? With its own fictional programming language like in that assembly video game ? With a mini PCI-E connector somewhere ?

To pre-digest the videos for the FPGA before putting them on a gigantic SD card, I could use ffmpeg to output a less compressed format like .avi or an .mkv and then erase the header and footer ?

Have a name (little Lebowski urban achiever is too long), and a format 100×80 (free Eagle max), and a rough layout (HDMI super close, USB next to FTDI and to flash memory, all the memory to the right equidistant to the chip). AND, some kind of transparent cover, a first for me, make it seem more like a legitimate product and would reduce the risk of short circuits from something conductive falling on the board. For the symbols on the keyboard, there is the Comodore 64 keyboard symbol set which is cool. Or some ancient symbols ??

I am now moving away from SDRAM, challenging and I’m not sure why I’m putting myself through it. The real interest is going to be decoding videos stored on the SD card and putting them on screen. I want to try to do it like the pros – drawing to the screen in the blanking period and using only one SRAM.

****

Still trying to resolve the A18 issue.

• I tried soldering another IO pin to pin 20, but this led to total chaos, none of the address pins working. I could have tried severing the link between the pin 20 and the SRAM but I don’t want to damage the board before I identify the problem (it may be in the code?).
• Trying to lower the size of the address counter to stop at 17 instead of going to 18.
• I connected to the rpi’s DEN and changed the code to work with it instead of the FPGAs display en (it doesn’t work anyways). It is cool as it is more likely to capture the image on the rpi if I understand correctly.

****

I am now trying some of the code I was dreaming about – modifying the input and output video stream based on other parallel data.

Here is one strategy based on two bits of the same color having an impact on recording and playback.

if (b[3]==b[2]) begin
a <= data_in;
end
else begin
a <= 8'b00000000;
end

I have the two memories working (excepted A18 on the second SRAM), and also tried reading DEN from the rpi. It makes some pretty funky glitches by touching the RAM pins with my hands !

Also check out the bitmap to program the FPGA :

`default_nettype none

module vga_sync_test(

input wire clk_in,
input wire reset,

input wire rec, // Direction of io, 1 = set output, 0 = read input

//RASPBERRY PI
input wire [3:0] r_in,
input wire [3:0] b_in,
input wire [3:0] g_in,
input wire DEN, // I SOLDERED A WIRE HERE TO ACCESS DEN ON THE RPI !!

//VGA OUT
output reg [3:0] r_out,
output reg [3:0] b_out,
output reg [3:0] g_out,

output wire h_sync,
output wire v_sync,

//SRAM

output reg [20:0] addr,
output reg [20:0] addr_copy,
inout wire [15:0] io, // inout must be type wire

output wire cs_3,
output wire cs_2,
output wire cs_1,
output wire cs_0,

output reg we_1,
output reg we_0

);

wire [15:0] data_in;
wire [15:0] data_out;

reg [1:0] toggle;

reg [15:0] a, b;

assign io = rec ? a : 16'bzzzzzzzzzzzzzzzz;

assign data_out = b;

assign data_in[1:0] = DEN ? r_in[3:2] : 0; // I SOLDERED A WIRE HERE TO ACCESS DEN ON THE RPI !!
assign data_in[3:2] = DEN ? b_in[3:2] : 0; // I SOLDERED A WIRE HERE TO ACCESS DEN ON THE RPI !!
assign data_in[5:4] = DEN ? g_in[3:2] : 0; // I SOLDERED A WIRE HERE TO ACCESS DEN ON THE RPI !!
assign data_in[7:6] = 2'b00;

assign data_in[9:8] = DEN ? r_in[3:2] : 0;
assign data_in[11:10] = DEN ? b_in[3:2] : 0;
assign data_in[13:12] = DEN ? g_in[3:2] : 0;
assign data_in[15:14] = 2'b00;

wire display_en;
wire [11:0] h_count;
wire [11:0] v_count;

localparam h_pixel_max = 1280;
localparam v_pixel_max = 960;
localparam h_pixel_half = 640;
localparam v_pixel_half = 480;

// CS: low to select, high to deselect

assign cs_0 = toggle == 2'b00 ? 1 : 0;
assign cs_1 = toggle == 2'b01 ? 1 : 0;
assign cs_2 = toggle == 2'b10 ? 1 : 0;
assign cs_3 = toggle == 2'b11 ? 1 : 0;

//SRAM address counter

always @(posedge clk_in) begin

if (addr == 0) begin
   toggle <= toggle+1;
end

if (reset) begin
   addr <= 0;
end else begin
   addr <= addr+1;
   addr_copy <= addr_copy+1;

end
end

//REC control

always @(posedge clk_in) begin

   b <= io;
   a <= data_in;
if (rec) begin
   we_0 <= addr[0]; //not sure why it isn't the inverse of addr[0] but that doesn't make the inverse on 'scope
   we_1 <= addr[0];
end
else begin
   we_0 <= 1;
   we_1 <= 1;
end
end

//VGA COLOR OUT

always @(posedge clk_in) begin
if (DEN) begin // I SOLDERED A WIRE HERE TO ACCESS DEN ON THE RPI !!
if (toggle==2'b00 || toggle==2'b01 ) begin
   r_out[3:2] <= data_out[1:0];
   r_out[1:0] <= data_out[1:0];
   g_out[3:2] <= data_out[3:2];
   g_out[1:0] <= data_out[3:2];
   b_out[3:2] <= data_out[5:4];
   b_out[1:0] <= data_out[5:4];

end else begin
   r_out[3:2]<= data_out[9:8];
   r_out[1:0]<= data_out[9:8];
   g_out[3:2]<= data_out[11:10];
   g_out[1:0]<= data_out[11:10];
   b_out[3:2]<= data_out[13:12];
   b_out[1:0]<= data_out[13:12];
end
end else begin
   r_out <= 4'b0000;
   g_out <= 4'b0000;
   b_out <= 4'b0000;
end
end

vga_sync vga_s(
.clk_in(clk_in),
.reset(reset),
.h_sync(h_sync),
.v_sync(v_sync),
.h_count(h_count),
.v_count(v_count),
.display_en(display_en) // '1' => pixel region
);

endmodule

From https://www.fpga4fun.com/VerilogTips.html:

• I need to initialize verilog counters !!
• Another way of selecting 4 bits in a vector : wire [3:0] thisis4also = myvalue[16+:4];
• It might be smarter to use a PLL than to take the external clock directly.
• I need to debounce all input buttons !

****

Check out shaders that take video as input :

https://www.shadertoy.com/view/ctsyzN

https://www.shadertoy.com/view/XtcSRs

****

Tried to make some vignettes of the new board to show the impedence matching :

I think I will order it in white with the meanders exposed like on the VGA spaghettini.

Color options (I’m leaning towards white or maybe green):

***************************

I am now thinking about how I will be able to share all that I am trying to learn about verilog and FPGAs in workshops. The bottleneck is programming the FPGA without special hardware.

OLIMEX has a link to a rasberry pi utility called flashrom that can program and read FLASH memory documented here : https://github.com/OLIMEX/iCE40HX1K-EVB/tree/master/programmer/olimexino-32u4%20firmware

These raspberry pi examples program the ice40 and looks simple :

• https://j-marjanovic.io/lattice-ice40-configuration-using-raspberry-pi.html
• https://github.com/plex1/raspice40

The steps have been automated here : https://notabug.org/sagaracharya/swarajya/src/master/hdl_to_hx8k/on_pi

Also for the rpi Pico : https://github.com/dan-rodrigues/pico-hx

I could knock off the 2232 FTDI and have made something like this: https://shop.trenz-electronic.de/en/TEM0009-02-FPGA-USB-programmer-JTAG-for-development-with-Microchip-FPGAs

Most interestingly, it seems like Arduino Uno could program an FPGA using a library like SPIMemory by Prajwal Bhattaram : https://github.com/Marzogh/SPIMemory/tree/v2.2.0

Finally, I could make a board like the gameduino that has an API for the Arduino to use to talk to the FPGA which handles fast screen drawing. This would mean everything could be done within the Arduino IDE.

EDIT* Come to think of it, even if the FTDI adds cost, it would make everything so much easier for a workshop – one piece of software and no extra hardware to program after for the participants. But when I plug it in it says USB device malfunctioned…(I also realized that I think I can forgo the RS232 connections between the FTDI and the FPGA and just connect it to the EEPROM and FLASH.)

EDIT* The OLIMEX code for Arduino is also not compiling and winIceProgDuino.exe (to program FPGA by sending serial commands to Arduino firmware I suppose) is not opening either.

EDIT*2 The Arduino sketch compiles but only for MEGA, Leonardo, and Micro so far (no UNO or NANO or MINI) but only after removing the iceprog.cpp file.

******************

Some thoughts on low-level versus high-level programming :

Something unsatisfying about making something from a pre-digested meta language (fast.ai for instance). Lost the feeling of ownership of the thing you’re making.

• https://projectf.io/posts/fpga-graphics/
• https://github.com/lawrie/hdmi_examples/tree/master

I have a month to work on a 45 minute lecture on my work at the Technische Universität München. I will also be doing a lecture at TU Darmstadt in November. I would like to use this opportunity to try to bring my video experiments into focus and incorporate it into my previous time-lapse projects.

This could take the form of a video series of me playing the prepared video buffer, possibly with explanations about what is causing what effect and demonstrative images / videos ? It could be contrasted with a “typical” workflow using the constraints of a software platform like photoshop? I could prepare this a similarly focused investigation of how the prepared piano altered sound, how Sonia Sheridan altered the photocopier, Paul Schafer made custom concrete music machines, etc.

EDIT* : I had a try !

• It’s kind of long and I also need to get a better top view.
• Adding text to describe what’s happening ?
• I also see that when I’m turning knobs the device is kind of hidden. I haven’t really designed the interface to be playable and to look good and be legible while being played.
• Looked into some other examples of video synth top down videos :

This is making me think more about the physical presence of my devices, and how I could incorporate more mechanical parts – instead of purely making electronics. I may have to play the game a bit more, make things that look like what they do and help people understand the associations I’m trying to make.

I could have micrometer heads for the potentiometers :

I could have fiber optic cables too :

I think if I every try to make a product though I would need to team up with someone who has skills I don’t.

***

Why make hardware ?

• it can be analog and digital
• it’s faster at doing things with video than software
• it can be custom
• it has a live-playable interface

***

What effects am I creating ? (check out Premiere to see what kinds of effects exist).

• Recording and playing things back at different speeds (video transposition), assigning to different color channels
• desynchronizing recordings with the screen sync so that they jump around
• recording videos side by side in memory so that they bleed over one another.
• Video collage and montage composer (video sampling, video looping), video plastifier, étude II, micro-montage, noise research, play, do and see, polyvideo layering, defamiliarizing of the image + reflecting the mediascape we inhabit, video as “palpable”, “nontheoretical”, and “experiential” (quotes from musique concrete wiki).
• The structure of the videos is based on the indexicality of the medium (the SRAM and how it stores). So the recording technique is also the synthesis technique.

Struggling to represent the painterliness of the raster videos without showing them as a video. It is completely different from my experiments with lines and triangles, and is less intuitive for me. An attempt at a kind of chronogram of a video :

It gives some idea of the range of images I guess?

Here are some notes I took about a year ago after visiting a painting expo that relate to my painterly video experiments :

• Layering
• Contour
• Surface
• Saturation
• Flow vs. Choppiness
• Roughness, relief 
• Edges versus centers
• Movement vs stasis 
• Enriching of detail
• Abstracting, cosmic making
• Fine lines versus coarse
• Exposure 
• Color fields
• Texture
• Deep friedness
• Films of cows, ocean. Stills of still life? Flowers, birds, drapes folding, mold, fruit, bones
• Color mixing vs melting vs meeting
• Paint viscosity (runny vs clotted)
• Direction of brush strokes 
• Contour
• Focus direction in canvas
• Translucent flesh, shine vs glow from interior, waxiness 
• Graininess 
• Composition, color pairings and form
• Foreground displaced to background vice versa 
• Meeting pattern planes 
• Lighting and shadow
• Illusion of depth
• Cloudiness 
• Turbulence

Check out this “glitch” video artist Jacques Perconte that Marc shared with me : https://www.youtube.com/watch?v=8_Xhu9Vx5XM

He works, since the 1990s, with compression and achieves a painterly, impressionistic effects and exposes them on immense projection surfaces.

Check out also Tauba Auerbach’s work :

Jack Whitten :

*************

Some quotes from Art21 series :

James Turrel – what you are perceiving is perception itself. We don’t receive the world around us we create it.

Jeff Wall – Art gives you an experience that alters something, it doesn’t tell you or convince you.

Jeff Wall – When I started photography there were potential energies in the medium that weren’t being realized.

Roland Barthes – The punctum points to those features of a photograph that seem to produce or convey a meaning without invoking any recognizable symbolic system.

Olafur Eliasson – Art provokes a negotiation : why I am seeing this the way that I am seeing it, what does looking mean? Instead of questioning the object you are questioning yourself. Art offers the opportunity for self-evaluation.

Tauba Auerbach – I want to learn things all the time, I want to understand the patterns behind things. I experience science through craft. With craft I try to cultivate sensitivity in a practiced, purposeful way. If you work with marbling you know just as much about viscosity and flow than a scientist, through your fingertips in a different way.

Tauba Auerbach – Ideally I want to make an image that has a tiny effect on all the future images that you see.

Tauba Auerbach – The pursuit of the sweet spot, cultivate the place of boundaries, limits of fraying, not hard edges.

Cindy Sherman – I don’t know what I’m looking for until I see it.

Richard Serra – Artists invent strategies, tools, techniques, that allow themselves to see in a way they haven’t seen before to extend their vision beyond the standardized classic reflex actions. These help us to see inside what we’re doing so we don’t get into a lock step notion of how to do what you do.

Louise Despont – If you’re always making work for someone, and not for yourself, maybe you don’t let yourself make the mistakes that are necessary.

Louise Despont – Each drawing is a series of tiny discoveries, it reveals/unfolds the drawing from total control. I own at most 1/4 of the drawing. The rest is something else, this is what’s exciting.

Louise Despont – It’s best explained in the drawings, words are clumsy to describe something like the concrete feeling of spirituality.

Liz Magor – My Studio is a space to reconcile dissonance, no one knows I’m here. When I’m not in my studio I want to be in my studio working. My tools are rudimentary. I’m here for pleasure but it’s not fun. Everyone should have a studio for mental health. I can filter out the noise and see the ever present under the radar stuff.

Liz Magor – I’m not an animist but objects have stuff in them that comes out. I try to resurrect these objects from the netherworld.

Liz Magor – The slowness of the material process matches the slowness of my thinking process.

Liz Magor – I’m creating an experience for looking.

Liz Magor – I give myself my own program, I give myself my own assignments. And art is the choices I make.

Liz Magor – Maintaining the conditions for this production, which is not very logical, uncalled for. No one is asking me to do this, I’m barely asking me to do this. To do this I have to overlook my making with the journey of the things into the world.

Liz Magor – After the casting I unwrap it like a little gift, there are surprises.

Elliott Hundley – This photoshoot is so elaborate but not because I want a certain effect, because I want to not control the effects, and have a layer of unexpected results. In relinquishing control, the piece gives me something back I didn’t expect.

Jack Whitten – I’m not a narrative painter.

Jack Whitten – I built a device to move large amounts of acrylic paint in one gesture.

Katherina Gross – Painting is not linear. The synchronicity in painting is compelling for your thought process. I’m trying to grasp some of those fast thoughts that are moving through my brain.

*************

Reading about the history of video synthesis.

From https://museumzero.blogspot.com/2013/12/its-all-baseball-nam-june-paik-starts.html)

Nam June Paik sees Taoist energy in working with the flow of TV video :

“To receive simultaneously the parallel flows of many independent movements is, as Paik pointed out at the time, a classical Taoist way of meditating: by becoming aware of everything going on in the present, you discover eternity right now.” 

“I love Chinese history, surprise, nonlinearity.  You know what judo means?  A way to be soft.  You let other guy do all the work.  I think in some Oriental way.  In TV I try not to be boss, to stay as small as possible.  So that seems to work. “ 

“So then when I started TV, the best decision I made in life is not really to go into TV, but to do work inside TV.”

“Imagine everything that exists is flowing, like the tao, in a perpetual motion, with endless waves, like the ocean.  We come from it; we go back to it.  Whatever surges forward falls back, so Lao-tse, who wrote the Tao Te Ching (On the Nature of the Way), urges us not to try too hard.  Relax; be like a baby; follow whatever path presents itself.  That is the way. ”

Not striving to fit yourself to some preconceived ideal, like a Buddhist or a Confucian; simply being, following breath wherever it blows.  In this sense, the television signal is like the tao; endlessly variable, continually reversing itself, dying, being reborn, it is never idle, yet it is so vast and perpetual that it often seems calm as the sea.

Beginning with whatever live programs came along, distorting them, then recombining his distortions like waves on the ocean surface, Paik created an indeterminate and endless show for the Galerie Parnass, in Wuppertal, Germany, in 1963.  

From Scanimate: The Origins of Computer Motion Graphics :

• This is about the history of television, these were the first ways to put text and make graphics on screen (Media Archaeology!). Nowadays visuals are gratuitous. What did we lose in the transition to digital ? The imperfections, the proximity to the functioning.
• Had a role in music videos, and news segments, so was part of culture.
• “Blooming” is the term for the glowing edges in CRT Scanimate.
• It’s real life artefacts. It’s like exploding scale models instead of GCI.
• They made cookbooks with the recipes of different effects that created while working with clients.

From https://wearethemutants.com/2018/01/09/a-sloppy-machine-like-me-the-history-of-video-synthesizers/

Like its close temporal and conceptual counterpart, the audio synthesizer, the video synthesizer was created iteratively by academics, artists, and tinkerers, then eagerly snatched up by the world’s biggest media producers once prototypes had proved their power and versatility.

• Started with experimental musicians like John Cage and la musique concrète.
• Early pirate TV station in NYC.
• Amiga supplants the Scanimate and analog synths.
• The 1967 Portapak release and it’s importance for activism and experimental art.
• Video comes from the root video of Latin video (“I see”).
• There is a relationship between images and waves  :

CC BY-SA 3.0, https://commons.wikimedia.org/w/index.php?curid=641492

This is so hard for me to understand but this somehow relates to chirping also :

By Drummyfish – Own work, CC0, https://commons.wikimedia.org/w/index.php?curid=77608151

More cool matrix math image modifications here : https://en.wikipedia.org/wiki/Digital_image_processing

Also this website which describes it all visually ! https://setosa.io/ev/image-kernels/

From Video Art : An Anthology :

• • The synthesizer let’s you see things that exist only in the mind’s eye.
  • visual ingredients
  • video synthesizers churn out…images based on their own electronic structure.
  • We make the image with our eyes and brain. It’s psycho-visual
  • video as concretized imagination.
  • video is surreal, the images are ephemeral products of micro electronic pulses.
  • “electronic imagery”
  • video is a medium which works with time

The Vasulkas

*************

Here is an attempt to describe what could be a model of a potential “practice” :

*EDIT* This should include me blogging ! Maybe add a RESEARCH and/or DOCUMENTATION phase ?

*******

Check out this pyramid of types of work :

I feel like my project is about analysing (and curating), I’m not sure if I take a real position.

*******

Check out this amazing NIME article called The Concentric Sampler: A musical instrument from a repurposed floppy disk drive by Timothy Tate about “the redundancy and physicality of magnetic recording media” which utilizes “time-based granular synthesis” and lo-fi:

https://nime.pubpub.org/pub/uh76shf0/release/1

Some quotes :

• Physical media offer an opportunity to “foreground the physical medium as a tool for musical expression.”
• “The deterioration of old magnetic tape as it is looped, defining a … musical structure.” The “failure of the medium is in focus, rather than the mechanism.”
• “as soon as something’s on tape, it becomes a substance which is malleable and mutable and cuttable and reversible in ways that discs aren’t.”
• “This study emphasises working within a medium’s limitation, rather than prescribing a compositional framework or sonic agenda upon it”
• Motivation to “foreground musical and technical possibilities…and generative sonic potentials…and novel, unique expressive and
• compositional possibilities”…to be “discovered…explored”
• The device is a “performable instrument and a generative sonic tool”
• “Rather than focusing on the authenticity of the sound reproduction, the Concentric Sampler draws focus to the byproducts and the resultant indexicality and generative sonic possibilities of the floppy disk as a medium.”
• “the term ‘musical expression’ here places value on the ability to shape and define a musical grammar from the indexicality of the …medium and mechanism.”
• “subverting traditional modes of … expression“
• “Each section is accompanied by a demonstrative video” !!!
• The live playable instrument can “achieve the dissociation of pitch and time“
• “imperfections in … reproduction”

• “possibilities within a framework of … making”

Now following up on some of the references from this article:

• You can think of an instrument as a framework that has a predisposed range (affordances). Our tools provide a certain range of suggested usages. Some things are easier and some things harder to do with an instrument, this is the instrument’s spectrum. If you stay within those ranges, you accept the silent grain of the instrument. If you make an unusual tool then, do you risk finding yourself in an unusual affordance ? (J. Mooney) Could it be possible to make videos subtractively, instead of additively ?
• From New Media Reader : The different between representation and simulation. P.18″Digital media process the physical properties of the input data, light and sound waves, are not converted into another object but into numbers; that is, into abstract symlbols rather than analogous objects and physical surfaces. Hence, media processes are brought into the symbolic realm of math rather than physics or chemistry. Once coded numerically, the input data in a digital media production can immediately be subjected to the math processes of addition, subtraction, multiplication and division…” AND compressed AND manipulated more easily than analogue forms because they are more mutable than objects. Also easy access and quick movement of the data of an enormous mass of data. This causes the materiality of the world around us to become unsteady…The televisual
• Because everything else is also digitized, there is a “convergence of previously discreet media forms, now a new fluid area of media decentralized production and consumption. Remediation, Multilinearity.
• Hand-made videos. Exploring the boundary between hand tools and large-scale machines which is a distinction Marx makes P.91.

Check out these Bauhaus era artist’s work with the audio band in video :

Paul Schaeffer (coiner of the “club d’essai“) designed specific tools like the morphophone and phonogène for modifying audio for musique concrete :

*******

Watching ENSCI diploma presentations I’ve thought about how nice the sequence is : first you write something that explores a topic and cites thinkers on the subject, and then you work on a design project that relates to this somehow. Also looking back at some videos, there is already a lot of content I have produced that I could try to learn from ! Like that Amsterdam-based artist told me, I could also focus on using my tools.

I am also doing a synth workshop in late September at Villette Makerz but I’m not sure if I can connect to that or not here. *EDIT* an FPGA board that generates patterns based on audio input is a GO !*

I also want to make a next FPGA board which will be a software reconfigurable device so that I can move to verilog for the summer instead of making a new board for every experiment. Not sure if this could also take the form of a simple video synth for Villette Makerz or at least a simplified version perhaps.

*******

Some quick looking in to GPUs :

GPUs are all about direct memory access (DMA) not mediated through the CPU. A thought about the FPGA board – perhaps I should first have Arduino mess with the clock while playing back / recording something on the 16MB board (but I’m limited to the number of pins for address and I/O – it would essentially be a counter that could change in frequency on the fly)? Having memory connected to the screen (a screen buffer) and modifying it is the fundamental computer display setup. From 1951 a memory pattern on CRT :

It would be cool to experiment with sprites and copying parts of memory from one bank to another too like a blitter https://en.wikipedia.org/wiki/Blitter .

It looks like what makes shaders cool is that they are programmable and have their own code languages now. Before shaders there were hardware rendering pipelines called fixed-function. Different units would be responsible for specific functions. It seems like these units would take in vertex data then output pixel colors.

I looked in to how to do matrix multiplication in hardware. It actually seems to be more natural as an analog circuit with resistor arrays. It can also be done by multiplying two 2-bit binary numbers using this kind of logic setup :

**********

I am becoming more and more curious about the difference from having a screen buffer that is written to during the blanking period and having a massive bank of memory that can be recorded to like in the 128Kbit. Check out these articles about how writing and reading to video memory is dealt with in different systems :

https://en.wikipedia.org/wiki/Tiled_rendering

https://en.wikipedia.org/wiki/Multiple_buffering

https://en.wikipedia.org/wiki/Vertical_blank_interrupt ,quoted from : 

“During the vertical blanking interval, the driver orders the video card to either rapidly copy the off-screen graphics area into the active display area (double buffering), or treat both memory areas as displayable, and simply switch back and forth between them (page flipping). [The two buffers are called the front and the back buffer] Some graphics systems let the software perform its memory accesses so that they stay at the same time point relative to the display hardware’s refresh cycle, known as raster interrupt or racing the beam.” [i.e. you can also draw things during the horizontal blanking interval]

**********

The Real-Time Corrupter is fascinating https://redscientist.com/rtc . The kinds of memory modifications it allows for are fascinating and far more dynamic than static, text-based find-and-replace experiments I’ve done in workshops. Looking at this video I learned some cool stuff (https://www.youtube.com/watch?v=n9HS6zftuSk&list=PLItZ3jvJKD7rnoxmqJJ0B5E1B9_WW9L5E&index=2). For instance, copying values from one address (in video RAM, scrolling backdrops memory space a.k.a. “nametables”, NES RAM, ROM etc.) and then reapplying them to another address every frame (called piping) or just one time, the ability to isolate specific effects with the sanitize function. It can generate noise between certain values, or shift values up or down on (called tilting), listen to a value and then reapply it after a fixed number of frames, freezing the current value somewhere for future frames, replacing values intelligently with values in certain sets (for 3D glitching). It’s like performing brain surgery while the patient is fully conscious and telling a story. All of these memory transformations could be applied with the FPGA board !

**********

In a similar spirit, this game called Code War involves creating a program that competes with others to write to all of the memory space. There are competing strategies (quoted from https://corewar-docs.readthedocs.io/en/latest/corewar/strategies/) for warriors :

Rock - a warrior which rapidly bombs the core with dat instructions
Paper - a warrior which replicates, creating multiple, parallel copies
Scissors - a warrior which scans the core looking for other warriors

The battle is visualized in a memory grid (https://corewar-docs.readthedocs.io/en/latest/corewar/visualisation/)

You can simulate and battle warrior code here : https://crypto.stanford.edu/~blynn/play/redcode.html

**********

Visualizing memory access in time. From https://bling.kapsi.fi/blog/x86-memory-access-visualization.html:

*********

Some thoughts on HCI from people at work :

it’s research if it follows scientific method and has possible applications.

Find your peers, try to publish in their journals.

The idea of publishing is to get feedback from your peers.

If you make a pedagogical tool, then you could test how effective it is at helping people learn.

Based on this conversation, I thought about how I don’t necessarily want to promote engineering education and that I always want to be on the design/art side of things. I also have learned that I find doing something I already know how to do less exciting, and so making simple kits or small series of artworks that are guaranteed to work for days on end, is not always super rewarding for me intellectually. This leads me to the current conclusion : I want to teach and then do a kind of artistic research on the side. I should then keep building my teaching career and try to get expos of my work. I am still trying to figure out how exactly my artistic research should be communicated (through articles in design magazines, through conferences with expos connected to them?).

**********

I am preparing a solar workshop at Villette Makerz based on the simple solar engine with optimized SMD components. The idea is an art bot that will draw, paint, in the sun. I am working on testing the various combinations of solar panels, capacitors and voltage supervisors.

We are also making a version 2 of the video synth modules which are all Eurorack compatible in terms of dimensions, use 3.5mm audio jacks, the eurorack power supply. The idea is that the modules be both manual and automatable for the purpose of demos and to be didactic for students learning about analog electronics.

Marc is doing a great job reimagining this project – he is good at compromising and imposing the vision of the final thing on each step of the construction. I am, in contrast, driven astray I think by my fascination by what “the machine itself wants to express”…

********

Finally getting around to testing the Arduino-controllable analog switch to activate record or READ mode on the SRAM 16MB board. The idea is to test taking a recorded video and then doing some bit manipulations with it and saving it back to the memory. Predictably though, I’m having issues just writing anything to the thing…

I/O pins on Arduino 0-7
CLK on Arduino 12
REC on Arduino 13 connected to analog switch connecting the WR pin on SRAM to either VCC or !CLK

unsigned long memory; //total number of 8bit words on the 16Mb SRAM = 2048000

const byte IO_0 = 7; 
const byte IO_1 = 6; 
const byte IO_2 = 5; 
const byte IO_3 = 4; 
const byte IO_4 = 3; 
const byte IO_5 = 2; 
const byte IO_6 = 1; 
const byte IO_7 = 0; 

void setup() {
//Serial.begin(115200);
pinMode(13, OUTPUT);
pinMode(12, OUTPUT);

pinMode(IO_0, OUTPUT);
pinMode(IO_1, OUTPUT);
pinMode(IO_2, OUTPUT);
pinMode(IO_3, OUTPUT);
pinMode(IO_4, OUTPUT);
pinMode(IO_5, OUTPUT);
pinMode(IO_6, OUTPUT);
pinMode(IO_7, OUTPUT);

//WRITE
while(memory<= 2048000){
memory++;

// if (memory%10000==0){
// Serial.println(memory);
// }

if (memory%5==0){
PORTD = B11110000; // the IO pins. simple pattern test.

}
else{
PORTD = B00001111;// the IO pins. simple pattern test.
}
//WRITE MODE
PORTB = B11101111; // PIN 12 ARDUINO CLK goes LOW/HIGH
PORTB = B11111111; // PIN 13 ARDUINO WR STAYS HIGH

}
// Serial.println("finished writing");
}

void loop() {
pinMode(IO_0, INPUT);
pinMode(IO_1, INPUT);
pinMode(IO_2, INPUT);
pinMode(IO_3, INPUT);
pinMode(IO_4, INPUT);
pinMode(IO_5, INPUT);
pinMode(IO_6, INPUT);
pinMode(IO_7, INPUT);

digitalWrite(IO_0, LOW);
digitalWrite(IO_1, LOW);
digitalWrite(IO_2, LOW);
digitalWrite(IO_3, LOW);
digitalWrite(IO_4, LOW);
digitalWrite(IO_5, LOW);
digitalWrite(IO_6, LOW);
digitalWrite(IO_7, LOW);

//PIN 13 REC IN LOW READ MODE
PORTB = B11011111; // PIN 12 ARDUINO CLK goes LOW/HIGH
PORTB = B11001111; // PIN 12 ARDUINO CLK goes LOW/HIGH
}

unsigned long memory; //total number of 8bit words = 2048000
byte cell; // store the word at this address

void setup() {

//PD0 - PD7 are IO
pinMode(13, OUTPUT); // REC - PB5
pinMode(12, OUTPUT);// CLK - PB4

 while(memory<= 2048000){
    memory++;
//READ
        DDRD = B00000000; // all IOs in INPUT
        PORTD = B00000000; // no pull-ups

        PORTB = B11011111; // WR stays LOW + CLK HIGH
        delayMicroseconds(10);
        cell = PIND; // read the cell at this memory address and store it in the variable cell
        delayMicroseconds(10);
        PORTB = B11001111; // WR stays LOW + CLK LOW
        delayMicroseconds(10);

//WRITE
       
        DDRD = B11111111; // all IOs in OUTPUT

        PORTD = ~cell; // write  a transformed cell back to memory
        PORTB = B11111111; // WR stays HIGH + CLK HIGH
        delayMicroseconds(10);
        PORTB = B11101111; // WR stays HIGH + CLK goes LOW
        delayMicroseconds(10);
  }
}


void loop() {
//READ MODE TO SEE WHAT WE HAVE IN MEMORY
        PORTB = B11011111; // WR stays LOW + CLK HIGH
        delay(500);
        PORTB = B11001111; //  WR stays LOW +  CLK LOW
        delay(500);
}
Not working either...

Heading towards a more reliable, deployable and software-leaning approach (but not so much about automated choreography as with previous atmega boards as augmented live playable machine for manual performances) to working with video now.

I am also trying to be a bit more strategic and attempt to think ahead a little bit beyond the one board one experiment situation. It takes a long time to trouble shoot a single board and learn all the lessons from it, I have to give each board the time it deserves and I need to be perhaps less productive and more thorough.

I am also coming to the awareness of what is my scope with this next board :

• I won’t be doing challenging engineering things (like implementing different ways of programming the same FPGA, interfacing with differential pair protocols like HDMI) that have no impact on the images and take loads of time to do.
• These are boards for experimenting and live playing, so they also need to have controls on the board.
• I also need to think about safety, avoiding the possibility of easily making short circuits and damaging the board.
• I’d also like to move back to color, and away from the intense limits of exclusively 1bit resolution.
• I want to keep removing superfluous cables and adapters too, this one will have only a VGA out.

I made a map of my prototypes so far for this project :

It’s been around two years I’ve been working on this !

After talking with Zach at work, his idea was to show not just the screen but also me turning knobs etc. Here’s what this could look like :

Or,

…or,

It would be nice to have a computer interfaced oscilloscope to record the signals.

*****

The most plug and play option would appear to already exist : a tiny raspberry pi zero can already run Processing scripts and control small screens https://learn.adafruit.com/processing-on-the-raspberry-pi-and-pitft/processing !

Here’s a good intro to making simple patterns with processing : https://processing.org/examples/

We would be more in the zone of software video synth : https://learn.adafruit.com/feather-rp2040-dvi-video-synth

Also seem to be companies making just this kind of thing : https://store.excamera.com/

Arduino talks to the FPGA by SPI as if it were a RAM space. https://excamera.com/files/gameduino/synth/doc/gen/poster.pdf

Design / Engineer friend Paolo Salvagione pointed me to Configurable mixed-signal ICs. It appears to be like an FPGA but for mixed analog and digital circuitry and is configured in design software.

There is also the world of ASICs and the google open-source silicon project https://developers.google.com/silicon

*************

My project was originally about slowing down computer processes and representing them in space. Now I just seem to order things on Amazon and design increasing numbers of PCBs. It seems that I have so little time to do the art in the end because of how much investment the technical stuff requires. How could I get back to my original project here ?

My project also had a collection of related techniques :

• Try to free machines from their corseted, factory settings and reveal their full range of expression that would otherwise just exist in a parallel unseen dimension
• Try to show our files from the perspective of / through the eyes of the machines that are processing them.
• Curate series of abstract formal compositions which emerge from figurative, architecturally-themed or culturally iconic ones.
• Try to describe the behaviour / idiosyncracies of algorithms and make them tangible
• Isolate specific moments of machine-to-machine interface in a larger system
• Get one’s hands inside the black box, and make prepared machines which expose their parameters
• Try to rebuild electronic systems based on help from the DIY internet and then hope to stumble on something unintentional
• All the while emphasize the materiality of technology
• Trying to go super low-level and avoiding abstract computer “visualizations”
• Exploring the link between visual chaos and harmony, that sweet spot of medium entropy.
• Riffing off of the music synthesizer movement of knobs and playful electronics interfaces and its anti-theory vibe
• Exploring the surreal, bizarre space of the computational unconscious
• Do “artistic research” projects that are educational, at least for me
• play with form versus content

I wonder if the pixel based screen is not really appropriate for my methodology. It’s the opposite of over-looked and black boxed. It’s an obsession for an entire culture. It also does a pretty good job of “representing” what happens inside the computer already. It doesn’t really need my help !

********

I also need to do a debrief on this leg of the video synth project. What have I learned ?

Technical stuff :

• • • How to make and debug PCBs
    • To work with video + SRAM with counters as well as some op amp circuits. The difference between digital and analog in the video context.
    • To work with the VGA protocols, about resolution and brightness of the image.
    • I learned about oscillation, the difference between KHz and MHz in the context of video and what sampling is.

Stuff about media representation

• • • some aspects of the nature of visual memory, how some of our sensory apparatus work at different speeds
    • the curious experience of “searching” for an image (like when messing with ADC knobs and CLK speeds).
    • what is required to identify / recognize and image or scene, how much resolution and shape
    • Deconstructing the illusion of television by interacting with its materiality and mutability
    • Repeating historical art explorations with television (see Sans Soleil – Chris Marker)
    • synchronizing the data with the frame of the image is a key part of the illusion of video. If you mess with this suddenly the video frame becomes a malleable object. If it is desynchronized, the image is out of frame and will jump around with the SRAM recording. If you change the speed of recording or of playback you can zoom.
    • Layering of different images in a palimpsest can create textures from them.
    • I’ve made some nice abstract pattern discoveries through knob twisting.
    • Exploring the gap between legible figurative image and abstract patterns, contours, fields,
    • the texture and grain of data at various scales
    • the connection between video and abstract field painting

What does it mean to be trying to make super simple hardware video filter in the age of AI generated video and images ? How is this activity relevant ? I feel like I’m looking for low hanging fruit here but I’m not sure there is any left. Also, the time it takes to make a single experiment in hardware is astronomical compared to the software option…

I think the project started off about the screen itself, how to send signals and display them. At some point it became clear that the screen just displays data stored in memory.

In this spirit, I could try to represent memory access patterns : https://en.wikipedia.org/wiki/Memory_access_pattern Or the patterns that memory is refreshed in : https://en.wikipedia.org/wiki/Memory_refresh

http://www.overbyte.com.au/misc/Lesson3/CacheFun.html

I could also sample images and then modify them algorithmically? But it kind of ends up looking like simple Photoshop filters. It would have to be modified in some way based on the way the image is stored in the memory ?

Check out this image stored in DDR ram decaying over time from J. Alex Halderman’s paper : https://jhalderm.com/pub/papers/coldboot-sec08.pdf

Also it seems like different DDR has different decay rates (from A Trustworthy Key Generation Prototype Based on DDR3 PUF for Wireless Sensor Networks https://www.researchgate.net/figure/DRAM-cells-decay-feature-with-power-switch-interval-time-of-120-s-a-DDR3-device-1-b_fig3_263586301):

For comparison, check out the same Mona Lisa image sent through the air and damaged by the earth’s atmosphere :

********

I’ve never thought of this before but I guess I could generate a simple arduino code, and then take the .hex file and glitch it with any of the glitching techniques I’ve been using and see what it puts on screen.

I could also test overclocking / overheating the atmel and seeing how they collapse !!

********

I should also finish the boards I’ve already designed and had made, they offer learning opportunities and possible discoveries ! The bucket brigade, the digitally-controlled pots (meh), and the band splitter (*EDIT* completed !) are the three that are left from that series. Also the Palimpsest.OS 2 board when controlled by microchip – especially if I can get the sync working ! Of course I have the new 128Kbit memory board (*EDIT* all done !) once I get the parts too and then a final (?) FPGA v2 board.

********

I am still interested in exploring FPGAs and getting my hands in the tech to possibly stumble on cool stuff though so here is a second attempt at a video FPGA board based on the iCE40HX1K-TQ144 to output HDMI, DVI, VGA, and composite video.

For generating verilog, there is migen for python 3 (https://github.com/m-labs/migen). I’m going to try a super simple thing in Verilog first to get a feeling for it. 

I am learning verilog here : https://hdlbits.01xz.net/wiki/Main_Page

It looks like generating HDMI is doable even though there is a difference between LVDS and TMDS (involving possibly 100nF series capacitors ?) :

Here is the official guide : https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/UZ/FPGA-TN-02213-1-7-Using-Differential-IO-LVDS-Sub-LVDS-iCE40-LP-HX.ashx?document_id=47960

https://www.fpga4fun.com/HDMI.html

blackmesalabs.wordpress.com/2017/12/15/bml-hdmi-video-for-fpgas-over-pmod/

https://github.com/hdl-util/hdmi/

Different chips being used like the PTN3360D HDMI / DVI Level Shifter (IN STOCK!), a TFP410PAP TFP410 TI PanelBus™ Digital Transmitter (NO STOCK!),

According to the datasheet, “The LVDS25E/subLVDSE differential output buffers are available on all banks but the LVDS/subLVDS input buffers are only available on Bank 3 ofiCE40 LP/HXdevices.” ***Those are INPUTS but there are no special OUTPUT pins.***

I have replaced the LDO with was giving me trouble previously and am making this version USB programmable so it could be a useful for others as a cool video kit.

*****

Revisiting FPGA programming, here is where I got to last time :

Here is my process for the FPGA programming so far :

1. I signed up for an account at www.latticesemi.com.
2. I got a licence for iCEcube2, put it somewhere easy to find and took note of the directory, and downloaded iCEcube2 and the Lattice Diamond software from here : https://www.latticesemi.com/en/Products/DesignSoftwareAndIP
3. I plugged in the iCEstick and it blinked in a circular pattern. I also checked that it had a port under Device Manager (it had 2!). 
4. I went into iCEcube2 then to Help > Tutorial to open a pdf called “Implementing the Design” and followed the following steps :
   1. Start new project (iCE40, HX1K, ?TQ144?)
   2. Add Design file iCElab.v and Constraint file iCElab.sdc and checked the Device Info.
   3. Run Synplify Pro Synthesis
   4. Select Implementation
   5. Add constraint file iCElab.pcf under Import P&R Input Files.
   6. Run Placer
   7. Check the Floorplan, package view, timing analysis, power estimation
   8. Generate the bitmap (.bit and .hex files) which is saved wherever the project was saved. (For instance C:\Users\Jonah\Desktop\FPGA LATTICE DEMO PROJECTS\quick_start\quick_start\quick_start_Implmnt\sbt\outputs\bitmap).
   9. Here is what everything should look like once finished :
   10. 
5. I then transitioned to Youtube for a detailed explaination of using Diamond Programmer with the iCEstick here : https://www.youtube.com/watch?v=Df9k1T0bHmA&ab_channel=Dom
   1. Launch Diamond Programmer and take the default options (or click scan and take those). Important to note that you must launch Lattice Diamond Programmer directly, not through Lattice Diamond, in order to find the iCE40HX1K chip.
   2. It will mistake the board for a JTAG interface and give the following errors : “Failed to scan board”, “Scan Failed – Creating Blank Programmer Project.”
   3. Now change the Device Family to iCE40, the device to iCE40HX1K, and under Program enter the following information :
      1. Change Access mode to SPI Flash Programming and now some other options appear. Select > Vendor: Micron, Device: N25Q032, Package:  8-pin VDFPN8
      2. Now load the bitmap (.bin) file and check that it has a non-zero datasize :
      3. 
      4. Click OK and then click the green traffic light on the next to top row of icons. You should then see a completion message and have the program on your board :
      5. 
      6. Presto !

Just for info :

For the actual pinout of the ice40 (which you can change in Pin Constraints Editor):

***

And here is my attempt programming my own board with the Lattice Programmer.

I followed the same steps as above but instead selected the HW-USBN-2B (FTDI) programmer. Important to note that you must launch Lattice Diamond Programmer directly, not through Lattice Diamond, in order to find the iCE40HX1K chip. Also note that you need Lattice iCEcube2™ Software, not just Diamond for some reason.

Here are the color connections needed from the Lattice Programming Cables User Guide :

The USB power and Board power lights should be on on the programmer and the Prog blue LED should flash a few times before the Done blue LED will flash and Lattice Programmer will display Operation: successful.

I am taking the example LED rotation verilog .v code :

module LED_Rotation(

    input  clk,
    output LED1,
    output LED2,
    output LED3,
    output LED4,
    output LED5

    );

               reg[15:0] div_cntr1;
               reg[6:0] div_cntr2;
               reg[1:0] dec_cntr;
               reg half_sec_pulse;                         

               always@(posedge clk)
                              begin
                              div_cntr1 <= div_cntr1 + 1;
                              if (div_cntr1 == 0)
                                            if (div_cntr2 == 91)

                                                           begin
                                                           div_cntr2 <= 0;
                                                           half_sec_pulse <= 1; 
                                                           end
                                            else
                                                           div_cntr2 <= div_cntr2 + 1;
                              else
                                            half_sec_pulse <= 0;                            

                              if (half_sec_pulse == 1) 
                                            dec_cntr <= dec_cntr + 1;                                          
                              end                                                            
               assign LED1 = (dec_cntr == 0) ;
               assign LED2 = (dec_cntr == 1) ;
               assign LED3 = (dec_cntr == 2) ;
               assign LED4 = (dec_cntr == 3) ;
               assign LED5 = 1'b1;
                                                     
endmodule

module vga_sync_test(
    input wire clk_in,
    input wire reset,
    output reg r0,
    output reg r1,
    output reg r2,
    output reg b0,
    output reg b1,
    output reg b2,
    output reg g0,
    output reg g1,
    output reg g2,
    output wire h_sync,
    output wire v_sync,
    output wire led,
    output wire locked_led
  );

wire clk_sys;
wire display_en;
//reg [9:0] h_count;
wire [9:0] h_count;
//reg [9:0] v_count;
wire [9:0] v_count;
assign  led = clk_sys;

localparam  h_pixel_max = 640;
localparam  v_pixel_max = 480;
localparam  h_pixel_half = 320;
localparam  v_pixel_half = 240;

//Check if we can create RGB colors
always @(posedge clk_sys) begin
  if (display_en) begin
    if (h_count < h_pixel_half
        && v_count < v_pixel_half) begin
      //Assign here your test color
      r0 <= 1'b0;
      r1 <= 1'b0;
      r2 <= 1'b0;
      g0 <= 1'b0;
      g1 <= 1'b0;
      g2 <= 1'b0;
      b0 <= 1'b1;
      b1 <= 1'b1;
      b2 <= 1'b1;
    end else if (h_count > h_pixel_half
            && v_count < v_pixel_half) begin
      //Assign here your test color
      r0 <= 1'b0;
      r1 <= 1'b0;
      r2 <= 1'b0;
      g0 <= 1'b1;
      g1 <= 1'b1;
      g2 <= 1'b1;
      b0 <= 1'b0;
      b1 <= 1'b0;
      b2 <= 1'b0;
     end else if (h_count < h_pixel_half
            && v_count > v_pixel_half) begin
      //Assign here your test color
      r0 <= 1'b1;
      r1 <= 1'b1;
      r2 <= 1'b1;
      g0 <= 1'b0;
      g1 <= 1'b0;
      g2 <= 1'b0;
      b0 <= 1'b0;
      b1 <= 1'b0;
      b2 <= 1'b0;
    end else begin
      //Assign here your test color
      r0 <= 1'b1;
      r1 <= 1'b1;
      r2 <= 1'b1;
      g0 <= 1'b1;
      g1 <= 1'b1;
      g2 <= 1'b1;
      b0 <= 1'b1;
      b1 <= 1'b1;
      b2 <= 1'b1;
      end
  end else begin
    r0 <= 1'b0;
    r1 <= 1'b0;
    r2 <= 1'b0;
    g0 <= 1'b0;
    g1 <= 1'b0;
    g2 <= 1'b0;
    b0 <= 1'b0;
    b1 <= 1'b0;
    b2 <= 1'b0;
  end
end

vga_sync vga_s(
      .clk_in(clk_in),         //12MHz clock input
      .reset(reset),           // RST assigned to SW1
      .h_sync(h_sync),
      .v_sync(v_sync),
      .clk_sys(clk_sys),       //25.125 MHz clock generated by PLL
      .h_count(h_count),
      .v_count(v_count),
      .display_en(display_en), // '1' => pixel region
      .locked(locked_led)      // PLL signal, '1' => OK
      );

endmodule

set_io b0 76
set_io clk_in 21
set_io led 99
set_io r0 81
set_io b1 75
set_io g2 91
set_io r1 80
set_io v_sync 87
set_io b2 74
set_io g1 95
set_io locked_led 142
set_io r2 79
set_io reset 2
set_io g0 96
set_io h_sync 88

$display("0.5 seconds");

run -all

module dut ( input clk ); 

`timescale 1ps / 1ps
module top_module ( output reg clk );

      dut instance2 (.clk(clk));

           initial begin
           clk = 1'b0;
           forever #5 clk = ~clk;
     end
endmodule

module top_module(
input clk,
input load,
input [511:0] data,
output reg [511:0] q);

always @(posedge clk) begin
       if (load)
           q <= data; // Load the DFFs with a value.
       else begin
          // At each clock, the DFF storing each bit position becomes the XOR of its left neighbour
          // and its right neighbour. Since the operation is the same for every
          // bit position, it can be written as a single operation on vectors.
          // The shifts are accomplished using part select and concatenation operators.

         // left                     right
         // neighbour              neighbour
           q <= q[511:1] ^ {q[510:0], 1'b0} ;
        end
    end
endmodule

`include "rule90.v"
`timescale 1ps / 1ps


module rule90_tb();
reg clk;
reg load;
reg [511:0] data;
wire [511:0] q;

rule90 DUT (
.clk(clk),
.load(load),
.data(data),
.q(q)
);

initial begin
#10
clk = 1'b1;
#10;
clk = 1'b0;
#10;
load = 1'b1;
data = 1'b1;
clk = 1'b1;
#10;
clk = 1'b0;
#10;
load = 1'b0;

end

always #10 clk = ~clk;
endmodule

Making things easier, simpler, more plug and play.

****

Workshop
Organize parts 

Palimpsest.OS
Get all channels working 
Get raspberry pi VGA out working 
Test with raspberry pi VGA put 
Fix VGA input/output (I know what the problem is at least :)!
SPI SRAM 
Get recording as fast as possible 
Try with 4MB FRAM ?
New board with several + raspberry pi + snake-like channel overwriting?

FPGA
Try simple VGA with LatticIce40
Solder FPGA board 

I’ve got a Raspberry Pi Zero outputting VGA nicely. On startup it launches VLC in fullscreen and plays a playlist of iconic film excerpts. I activated hotplugging so it keeps looping even if the adapter is unplugged for long periods of time.

I used Win32DiskImager and downloaded the ISO Image Raspberry Pi OS with desktop (around 1GB) from the officiql website (https://www.raspberrypi.com/software/operating-systems/) and put it onto an 8GB SD Card.

In terms of connectors I needed a SD Micro > SD card adapter, HDMI mini > HDMI, an HDMI > VGA, a USB A > USB Micro for power, and a USB Micro to USB A female in order to plug in a mouse / keyboard.

I followed these three tutorials for setting up VLC autoplay and turning off annoying VLC text:

https://forums.raspberrypi.com/viewtopic.php?t=17051

Raspberry Pi: Run VLC on startup and play slideshow videos/pictures from folder

https://www.shellhacks.com/raspberry-pi-force-hdmi-hotplug/

Now adding a power off button (not good to pull the plug while running)

https://howchoo.com/g/mwnlytk3zmm/how-to-add-a-power-button-to-your-raspberry-pi

**EDIT The rasbpi turns off when I unplug HDMI or plug into the palimpsestOS. Is it because RGB are mixed with only 100ohm resistors ? Should I have 3 blocking caps and then mix after ?

Here’s a write up on how to VGA :

https://chipnetics.com/tutorials/understanding-75-ohm-video-signals/

Looks like parallel 75ohm resistors going to GND from the input is good practice + a cap and 75 ohm resistor on output?

VGA OUTPUT examples :

If I understand this last one, three parallel 75ohm resistors makes a 25ohm resistor. 97ohms gets 80% of 3.3V gone before the 25ohm dissipates the rest so that there is 0.7V left for the 3 channels. For a 5V supply like mine, I’ll need to remove 86% of 5V to get it down to 0.7V.  A 160 ohm resistor then ?

VGA INPUT examples :

*EDIT Made the changes (RGB colors in to GND through 75ohm, one color through cap to bias + 160ohm and now there is no output…But maybe it was already broken at this point? Can test when new converters arrive.)

Looked at some VGA in/out boards I had in my possession and saw the following :

• H and V sync can go to a 74HC125 Line Driver / Buffer.
• Color returns can be conected together and grounded along with chassis.
• Examples of color pins going to grounded 75ohm resistors then on to blocking caps. Also colors to gates of transistors.
• Colors also going to video signal switcher like this : QS4A210 – 2-Channel 4:1 Analog Mux/Demux
• Definitely DO NOT ground pin 9 (which is 5V), as I have done in all previous boards…

****

An older HDMI to VGA converter broke so I opened it up to see if I could reproduce it. It’s an ALGOLTEK AG6201 which appears to be not accessible anywhere but the manufacturer’s website.

The alternative is using a video chip which can trasmit HDMI like this project : https://hackaday.com/2019/07/26/hdmi-from-your-arduino/ which uses a CH7035B HDMI encoder.

Alternatively I use the HDMI to VGA adapter and solder a D Sub Standard Male connector (https://www.mouser.fr/ProductDetail/TE-Connectivity-AMP/2301843-1?qs=rrS6PyfT74crws9wAQVNoA%3D%3D&mgh=1&vip=1&gclid=Cj0KCQjw27mhBhC9ARIsAIFsETE7Rp9JFGXhYFAXh_Z2YbQUB2NfHqO8rM7yPueb-T3yFiKbUMvJkOEaAtjJEALw_wcB) to the board.

***

I will be testing a pico projector and a VGA capture device soon…

***

Trying again with SPI SRAM

This code seems solid to me but I can’t go beyond 100Hz…

#include <SPI.h>
#include <SRAM_23LC.h>

// SPI bus can be SPI, SPI1 (if present), etc.
#define SPI_PERIPHERAL    SPI
#define CHIP_SELECT_PIN   8

/* Device can be:
 * 128KB: SRAM_23LCV1024, SRAM_23LC1024, SRAM_23A1024
 * 64KB: SRAM_23LCV512, SRAM_23LC512, SRAM_23A512
 * 32KB: SRAM_23A256, SRAM_23K256
 * 8KB: SRAM_23A640, SRAM_23K640
 */
SRAM_23LC SRAM(&SPI_PERIPHERAL, CHIP_SELECT_PIN, SRAM_23LCV1024);

// Additional SRAM chips
// SRAM_23LC SRAM1(&SPI_PERIPHERAL1, CHIP_SELECT_PIN1, SRAM_23LC512);

#define START_ADDRESS   0

//uint8_t buffer[BUFFER_SIZE];
//#define BUFFER_SIZE  320

char buffer[1000];
#define BUFFER_SIZE  (sizeof(buffer) / sizeof(uint8_t))

void setup(void)
{
  pinMode(2, OUTPUT);
  /* Without parameters, begin() uses the default speed for this
   * library (12MHz for samd, 14MHz for sam, and 4MHz for avr).
   * Note that SPI transaction support is required.
   */
  SRAM.begin();
 // SRAM.begin(8000000UL);      // or specify speed
  //Serial.begin(9600);
}

void loop(void)
{
  //while (!Serial); // Wait for serial monitor to connect

// Record a series of values
  for (size_t i=0; i < BUFFER_SIZE; i++) {
    //buffer[i] = byte(digitalRead(A2));
        if ( (PINC & (1 << PINC2)) == (1 << PINC2) ) { //PC2 is what we're reading
        buffer[i] = 0xFF;// pin is high
        }
        else {
        buffer[i] = 0x00;// pin is low
        }
  }
/*
  // Print buffer to serial monitor
  Serial.print("Write Block: ");
  for (size_t i=0; i < BUFFER_SIZE; i++) {
    Serial.print(buffer[i], DEC);
  }
  Serial.println();
  */

  // Write block
  if (!SRAM.writeBlock(START_ADDRESS, BUFFER_SIZE, buffer)) {
    //Serial.println("Write Block Failure");
  }

  // Clear buffer
  //memset(&buffer[0], 0, BUFFER_SIZE);

  // Read block
  //Serial.print("Read Block:  ");
  if (!SRAM.readBlock(START_ADDRESS, BUFFER_SIZE, buffer)) {
    //Serial.println("Read Block Failure");
  }

  // Print buffer to serial monitor
  for (size_t i=0; i < BUFFER_SIZE; i++) {
    //Serial.print(buffer[i], DEC);
   if(buffer[i] == 0x00){
     //digitalWrite(2, LOW);
      PORTD &= ~(1 << PD2);    // set pin 2 of Port D low
   }  
   else{
    // digitalWrite(2, HIGH);
      PORTD |= (1 << PD2);     // set pin 2 of Port D high
   }
  }
  //Serial.println();
  //delay(1000);
}

I just can’t manage to get the same level of control with an SPI device as with parallel SRAM and counters.

****

New board time 😀 ! Test new things but keep the plug and play idea from last board and make even more so. SPEND MORE TIME SANITY CHECKING THE DESIGN and double checking pull ups and downs.

Goals :

• How about using a 16Mbit SRAM to store 128MBits of data with only a few added components ?! The plan is a pair of shift registers to convert serial output from a comparator into 8 bits to be sent all at once to the SRAM and the inverse on the output side. I would need the shift register clocks to be 8 times faster than the SRAM I think?
• Make it so power (5V – with an LDO on board to eliminate possibility for accidents) can be shared with a double power jack. Reverse polarity protection.
• A fine and coarse threshold selection !
• proper VGA input and output good practices that will never harm anything sending video signals in or recieving signals sent out (blocking caps, 75 ohm impedence matching, Vref for top side of variable comparator bias!!, buffers for H and V sync!!, two cables close together!! and shielding – guard rings? – on the PCB for these traces!! different grounds for different parts of the VGA cable, use BNC connectors for RGB??)
• Raspberry pi as input VGA through converter which plugs into a male VGA on the board, add an OFF/ON switch to safely turn off
  
• pass thru VGA signal switch !!
• Have different clock cans to switch between?
• Extended Display Identification Data chip as a test?
• Have audio out option ?

Here’s the preliminary circuit :

From https://www.cs.unca.edu/~bruce/Fall11/255/Labs/Lab13AnalogInput.html

From https://electronics.stackexchange.com/questions/144530/circuit-for-a-coarse-and-fine-setting-potentiometer

****

As for PCB inspiration, perhaps something that evokes the computer video graphics card :

Rectangular, with metal bracket (these are called Computer brackets in the Circuit Board Hardware – PCB category of Mouser.fr. They come in low profile or high profile), fan, heatsink, memory bank in a row, name of the board somewhere, PCI connector

****

Here is my first attempt at simulating the logic :

The only tricky part was activating parallel load of the output register only once per 8 clock cylces.

This design includes a giant FPGA to control enables all broken out along the PCI-E connector (that could be played like a piano with an alligator going to GND) in time and also to match the aesthetic of the video card. It would feature a stunning 128 Mbits (16MBits SRAM x 8) of memory. Would be cool to have LEDs next to each memory which light up when that block is recording.

***

Building on the idea of making physical artefacts, Vivien Roussel had the idea of moving towards displaying the chassis of the computer along with these boards. There are loads of cool test bench computer cases that could be an inspiration for this :

****

Or a DDR SDRAM module as inspiration :

Here’s what it’s looking like in Eagle so far :

I still like the idea of a kind of piano controlling :

• 3x SRAM CS sel bits
• 3x COUNTER EN + individual RST

And of course :

• Threshold control (fine and coarse this time !)
• Clock DIV
• REC/PB

Here’s the board as ordered :

CIRCUIT DIARY :

• The fine and coarse pots appear to work very well.
• The clock divider works as expected. Though it might be interesting to be able to play with different frequencies too as it seems to be important to get the combination of sampling versus pixel frequencies.
• I checked and the serial clock is indeed being divided by 8 and inverted (albeit super noisy!) :
• The Overflow and CS signals appear to be working well (though I had a hard time soldering the resistor networks!)
• The !WR signal is as expected
• Possibly should have put pull-downs for the SRAM I/0 pins ?
• I should have made a timing diagram not just the simulation..
• The option to manually advance the OVERFLOW signals is cool because you can solder one SRAM and test only it without having to wait for its turn to come around !
• I have reached a problem : the 596 is not shifting the serial into parallel. I can see it trying (little mini signals getting through), but it is as if the I/O pins are being pulled low, but by what ? The SRAM ? I’ve confirmed we’re in write mode so they should be high Z. The Serial to Parallel converter somehow? But the I/O pins are inputs for this IC…Hmmm. Is it something to do with the open drain outputs (or the Schmitt trigger inputs?) on the 596 ? **EDIT : Had a 595 with the same footprint and substituted it, seems to be working now.
• So, the output is very stripey. I have removed the 75ohm resistor to ground and shorted the 100ohm to the output RGB pins. I’ve tried shorting the blocking cap and it makes things a tiny bit easier to see but overall it is barely legible as an image. I think it has something to do with the output parallel to serial conversion. Here is a sample of a capture :

• For some reason it can also work much better :

• I don’t understand how it is possible to see the screen while it is recording as there is no “pass-thru” option…. There is also sometimes quite a difference from what is somehow passing through while in record mode and what plays during PB mode. *EDIT*There is a noise issue, when the VGA input is plugged in there is static that is entering somewhere. Trying to locate it currently. *EDIT* it is coming from the VGA IN. Tried connecting a bunch of GNDs (digital GND, chassis GND, color return RED) but still getting nowhere trying to eliminate the noise.
• I ordered the wrong type of bracket, this one is for a double row VGA…
• I had an issue with SRAM D but then replaced it and all is good.
• I forgot to have a pre-amp before the comparator, this is essential otherwise you don’t get any in screen peaks and basically don’t see anything unless you’re really lucky. I used the Palimpsest.OS preamp and bias setup and it works fine.
• The tiny trimpots need to be replaced with actual knobs !!
• I forgot to add loop LEDs ! It would have also been cool to know which SRAM is currently recording.
• EVERYTHING IS WORKING I CAN’T BELIEVE IT. The solution was to just test everything with a simple ramp using the function generator and look at the play back. Then I checked the pins on the SRAM and saw funky signals for several address pins that looked like they were several signals being added together. Clearly when I soldered in a bunch more SRAM and there were tiny connections between five different address pins and an I/O that I did not notice. This was causing chaos. I found the connections and fixed them, now it’s recording just as expected and it’s so glorious. NOTES : I am using the op amp from Palimpsest.OS AND crucially, am connecting both Analog and Digital Grounds between the two boards and the VGA IN with VGA OUT.

***

While waiting for this board to arrive :

• Try different function generated patterns of hitting count 0 enable while recording on the 16Mbit version
• Test the 8 layer board ! *DONE*
  • Remove pin 9 GND and fix other issues with VGA in and OUT with VGA beakout PCB
  • Test on raspberry pi / computer IN *DONE*
  • Test feedback ! *DONE*
• Try mini projector *DONE*
• Try VGA capture device *DONE*
• Put restart button on rasbpi

*******************

*EDIT* It works with rasbpi when I connect only a color, GND, H and V syncs !! So much more convenient than previously.

• It might be cool to be able vary the mixing of the different channels
• The output image is quite faintweak, I think I should rexamine the resistors I put at the termination and maybe switch to B+W.
• It’s a bit muddy with several channels, would be cool to be able to filter that
• I need a path to feedback with a pot !
• Switched the output resistors to a 150ohm going to R,G,B and it works nicely.
• Dip switch hard to use without tool.
• Hard to see which direction switches are pointing in darker light

More technical ERRATA :

• Pin 1 of the 40MHz clock should be pulled HIGH to be enabled, not LOW as it is on the board !
• The THRESHOLD pot isn’t connected to GND on one side…
• I should have tied the CCLR (pin 10, which resets when pulled LOW) of the 590 to VCC with a 10K instead of leaving it floating connected to VSYNC. This made it malfunction.
• BIG PROBLEM : I ordered multiplexers (unidirectional) instead of analog switches (bidirectional) ! The ‘157 multiplexers mess with SRAM B’s I/Os when it is in READ mode (when the SRAM is outputing values on the I/O pins). I ordered a replacement that is pin compatible, the 74LVC1G3157 (DATASHEET : https://www.ti.com/lit/ds/symlink/sn74lvc1g3157.pdf?HQS=dis-mous-null-mousermode-dsf-pf-null-wwe&ts=1679316452048&ref_url=https%253A%252F%252Fwww.mouser.de%252F). EDIT* The new components work perfectly – everything is good !
• The Sync Clock IC is 3.3V not 5V…
• Image jumps around of course. When I try to record with the Burst AND IC which outputs !CLK, no writing can occur. I’m guessing this gate messes with the timing somehow? As a workaround I’m trying to connect the 4 AND’ed V SYNC counts to either the address counter IC Reset or to another reset somewhere. 
• Lots of noise on V SYNC, I should maybe have made the input and output VGA jacks right next to one another…
• Pin 9 of the VGA D-SUB 15 is VCC for the Display ID EEPROM chip – but I have it connected to GND !! In general I need to respect the rules around the different grounds and return pins in the VGA protocol and not just connect them all together. Hoping to fix this in the next version.

***

Thinking about making a board with a small 5″ screen / or a mini projector incorperated in it

Fabien suggests using an LCD driver from a normal sized computer screen for a smaller screen (but he says it will will in 16:9 format). The other option he suggests is to use an FPGA to control a screen directly with LVDS.

Artist Andreas Gysin’s LCD 1 from http://lcd.ertdfgcvb.xyz/

***

Just realized that I could have an raspberry pi using VGA directly from I/0 pins : https://fr.pinout.xyz/pinout/dpi#

****

Currently thinking the next PCB should be raspberry pi sending video through I/O (not through HDMI) and FPGA controlling SRAM. This would allow messing with the sequence of the memory recording / playback. Could make a compact version of this project (a kind of black box, deployable version) without many external components but with sililar functionality. I could test making the FPGA USB programmable board too. Of course it would also be programmable.

To get here :

• make the automated palimpsest.OS board
• make the simple FPGA VGA board

****

I am revisiting the SPI SRAM code with renewed patience, I actually wrote it first on paper !

Here is my simple buffer filling code first off :

const int buffer_size = 2000;  // Only 2K bytes of SRAM on the 328P
byte buffer[buffer_size];
void setup() {
  DDRC = 0b00000000;  // set PC2 as input pin
  DDRD = 0b00000100;  // set PD2 as output pin
}

void loop() {

  //  fill the buffer
  for (int i = 0; i < buffer_size; i++) {  // iterate through buffer
    for (byte mask = 0b00000001; mask > 0; mask <<= 1) {  // iterate through a bitmask
      if ((PINC & 0b0000100) == 0b00000100) {  // if input pin high...
        buffer[i] = (buffer[i] | mask);  // set this bit
      }
      else {
        buffer[i] = (buffer[i] & ~(mask));  // clear this bit
      }
    }
  }
  // read buffer back
  for (int i = 0; i < buffer_size; i++) {  // iterate through buffer
    for (byte mask = 0b00000001; mask > 0; mask <<= 1) {  // iterate through mask
      if ((buffer[i] & mask) == mask) {  // if bit in buffer is high...
        PORTD |= 0b00000100;  // ...write output pin high
      }
      else {
        PORTD &= ~(0b00000100);  // else, write output pin low
      }
    }
  }
}

I tried the mini projector but it didn’t like the signals I was sending it. I think I have to avoid intelligent interfaces that can decide to send or not along my signals. Wondering about the camcorder CRT viewfinder and if I should head back in that direction.

Here is a popular 4″ screen :

Inspired by the history of mounting circuits on wood with screws and wire, evoking John Cage’s prepared pianos. 

This iteration of the project is born of a few realizations :

1. VGA is an analog signal, it’s not digital.
2. The coolest effects are the simplest ones : XOR, HP and LP filters, comparators, etc. which can be easily made with discrete components.
3. A simple low frequency oscillator could control these effects with an LED > LDR voltage controlled resistor set-up. 
4. Two out of sync oscillators easily make a pattern that doesn’t repeat often and is difficult to predict.

Pedagogically and aesthetically I like this idea : it goes back to the basics of electronics, the history of electronics, and will show the materiality of video signals. This in contrast to the overly complex use of digital components to do basic modifications…

The three basic circuits :

*TESTED* This works (powered at 5V, with pull down 10K on input and the rest 1K and two BD135s) at lower frequencies (<100KHz) around 5V.  I added a 5K variable resistor (or an LDR + resistor) to increase the resistance of R1 and it varies the threshold !

*TESTED* Works using BD136 PNP, 10K for the pull down and 1K for the base protection. General purpose diodes. I replaced the pull down with a 5K variable resistor and got some messed up results in the MHz. Doesn’t need power – just takes it from the input signal ! (But VGA signal would need to be amplified in order to work. 

*TESTED* With a 104 cap and 5K variable resistor I can vary the filtering of a 5V function generator signal. 

****

OK we’re back to the original plan ! Here is the Palimsest.OS Rev.2 :

WHY ?

• This board is for the inauguration of the IFT at the DVIC. It has to demonstrate technical proficiency on behalf of the staff, and must run independently as an tech-art installation, modifying video independently day in day out. 
• Rev.1 didn’t work for microchip automation, this one should work smoothly(?). If everything works I could write code that executes different video manipulations. I also added selection LEDs to show the microchip doing its thing.
• This tests the 8 channel 1-bit WRITE/REWRITE memory idea (but not the more elegant SRAM + buffer idea of Fabien), with certain effects tied to certain channels
• Incorporates a simple to control XOR, comparator and HP/LP/BP filter into one board
• Has a stable clock setup with metal can oscilloscope, a gen lock IC, and V SYNC burst setup
• Tests an (expensive) programmable filter IC
• It is a test for a simpler, inexpensive 8 ch recorder board that could be a cool kit
• Does away with the ADC and all its pesky issues and trades it for a simpler 1bit “ADC”. 
• I’m also using 5V SRAM to avoid the headache of different logic levels (though this means I only have 4MB of SRAM versus 16MB).
• For testing purposes it can be soldered as a logic-controlled board or as a physical switch controlled-board. 
• Instead of having lots of jumpers for wires, I went for rotary switches to make things more plug and play. However this also means that there are fewer experminental tests that are facilitated (like disabling a single counter while recording etc.) that were possible on rev.1
• Can layer different recorded portions easily in theory
• Battery switch and edge potentiometers instead of knobs
• Theoretically could do feedback and echo tests with this board as it can read and write from and into memory simoultaneously 
• This board should be easier to work with than the previous stacked PCI-E motherboard design which made knob turning and mounting hard. 
• Instead of using generic octal logic ICs I went for more specific purpose ones.
• The board will be made at https://aisler.net/ instead of JLCPCB so I’m hoping for a really nice finish

Here’s a possible minimal installation with it :

****

PALIMPSEST.OS v2 ERRATA :

• Pin 1 of the 40MHz clock should be pulled HIGH to be enabled, not LOW as it is on the board !
• The THRESHOLD pot isn’t connected to GND on one side…
• I should have tied the CCLR (pin 10, which resets when pulled LOW) of the 590 to VCC with a 10K instead of leaving it floating connected to VSYNC. This made it malfunction.
• BIG PROBLEM : I ordered multiplexers (unidirectional) instead of analog switches (bidirectional) ! The ‘157 multiplexers mess with SRAM B’s I/Os when it is in READ mode (when the SRAM is outputing values on the I/O pins). I ordered a replacement that is pin compatible, the 74LVC1G3157 (DATASHEET : https://www.ti.com/lit/ds/symlink/sn74lvc1g3157.pdf?HQS=dis-mous-null-mousermode-dsf-pf-null-wwe&ts=1679316452048&ref_url=https%253A%252F%252Fwww.mouser.de%252F). EDIT* The new components work perfectly – everything is good !
• The Sync Clock IC is 3.3V not 5V…
• Image jumps around of course. When I try to record with the Burst AND IC which outputs !CLK, no writing can occur. I’m guessing this gate messes with the timing somehow? As a workaround I’m trying to connect the 4 AND’ed V SYNC counts to either the address counter IC Reset or to another reset somewhere. 
• Lots of noise on V SYNC, I should maybe have made the input and output VGA jacks right next to one another…
• Pin 9 of the VGA D-SUB 15 is VCC for the Display ID EEPROM chip – but I have it connected to GND !! In general I need to respect the rules around the different grounds and return pins in the VGA protocol and not just connect them all together. Hoping to fix this in the next version.

More Meta errata :

• It’s a bit muddy with several channels, would be cool to be able to filter that
• I need a path to feedback with a pot !
• Switched the output resistors to a 150ohm going to R,G,B and it works nicely.
• Dip switch hard to use without tool.
• Hard to see which direction switches are pointing in darker light

Oy vey ! I realized that I could just use an I2C RAM IC and save about a billion components. Here are the more plug and play simple boards I made in the aftermath :

Good news: The 328 works. 

ERRATA : I fried the logic chips with 5V :(. Resoldered new ones and looks good.  I think I need to be feeding in a signal that has already been digitized (like by a comparator). Otherwise I need to mess around with knobs to get the signal right around the threshold of the logic gates with bias setup. 

Good news: The 328 works. And I can see the effect of selecting different filters. I’m not sure why but it works best when the signal is coming in on A and I’m taking the output on B (or vice versa). I’ve also got a cap going from the output of the filter board before amplifying it again.

ERRATA: I ordered the wrong length of bussed resistor network. 

Good news: The 328 works. 

errata ^ Wrong footprint (and value!) for the digital potentiometer here… Will have to wait for the correct part to test this.

Good news: The 328 works and at least it produces an image !

errata ^ H SYNC and V SYNC plugged in to wrong pins on Arduino (should be PD3 and PB1 respectively).

Good news: The 328 works.

ERRATA : the PD pin (which enables ADC IOs when low) is pulled HIGH ! I resoldered it and now it’s working great. 

I chose a non PWM pin on the atmega to be the voltage control pin of the VCO… I soldered it to the nextdoor pin which can do PWM and all is good. 

ERRATA: I tried two chips, they both come up as unidentified FRAM when I have them speak on the serial running the demo codes…I should probably pull Write Protect (WP) HIGH just in case. Still not working…I will try replacing with a 23LC1024 serial SPI SRAM as it has the same pinout. 

***EDIT: Just saw this on the Adafruit website : “For the 4Mbit version, you should change this to: fram.begin(3)”…Still doesn’t work though.

I replaced with the 23LC1024 and am using the SRAMsimple libary which appears to work well. For some reason the digitalRead I’m doing in the setup is always returning 0 even if connected to 5V.

#include <SRAMsimple.h>
#defineCSPIN8       // Default Chip Select Line for Uno (change as needed)
SRAMsimple sram;       //initialize an instance of this class
/*******  Set up