Author: marrs

I’ve made a new board to help students mess with video signals :

The idea is to insert a half-sized breadboard in the middle of the board to do experiments. An rpi zero in DPI mode is attached on the left hand side. The board lets students easily interface with the colors either in bit form or in mixed form (controlled by the DIP switches), it powers the rpi, it has VGA connector built in along with three amps. I’ve also ordered some comparators (LM2903P) and a simple ADC (AD7819YNZ) in throughhole packages. The idea is for me to do as little as possible and for them to get to have the fun of doing cool things. I have M2 holes for spacers to give this thing feet as the RPI in on the underside (but has an extra high header so the pins will be exposed in case the students want to connect to them). Hopefully they make mistakes and it creates cool outcomes !

I would like to make another version of this board which is just an OV7607 camera sensor with an Arduino and an FPGA. The idea would be that you could change the parameters of the camera sensor by uploading a new Arduino code, and that the FPGA would take the video data and convert it to VGA. This would in theory give students a lower level experience of video. First, they could modify the camera’s lens itself. Second, they could change it’s parameters (color balance, gain, etc.). Third, they can mess with the VGA signals coming from the FPGA (as in the board above). It would also be cheaper – no rpi but would need an FPGA – however it would not automatically play videos.

Here’s the board soldered :

I’m going to copy the SD card 10 times once I’ve got it setup for a rpi zero 2W. I forgot to order 64K resistors.

It has already made some nice fuzzy images from the rpi splashscreen :

*****

The workshop itself using this board was not especially smooth….

The rpi zero 2W that I ordered didn’t work with the same config.txt file to get the video out on the 40 DPI pins. This despite many frantic attempts and copy and pasting things on the internet, help from students using chat GPT, and attempts at doing things properly by using overlays. This is so typical of rpis in my experience… Also, for the zero you need so many things – beefy power supplies, the USB micro to USB female (and a splitter really), the mini HDMI adapter. The whole thing is just not really adapted for a workshop.

When testing on my rpi zero 1.2 (which is now fried) and their working boards the results were cool though. 

The students soldering the boards did not have universal success. A few successfully got one or two colors working, one got all three, and a couple students didn’t get their boards working by the end of the day.

We moved to using VGAX and Arduino, which they picked up fast. Putting the colors through the amps on the board did not really work so the boards were abandoned. Some students made some very nice animations, some had clearly used chat GPT. We weren’t able to convert an image and show it on the screen so far. 

I’ve introduced the possibility of using hardware components to modify the video but apart from an LDR and a potentiometer no one has made any filters of used any XORs. There have been takers for the function generators though and several students have used the VGA recorder. I am planning on the final day to show them examples of hardware modifications.

UPDATE : At the end of the week I tried again, first by identifying the specific version of rpi that I had on my rpi zero and then tracking down five rpi zero 1.1. What ended up working was coping the entire SD card exactly and using the rpi zero 1.1. However by this point the week was gone and the students weren’t motivated to begin experimenting with the working boards. They did find it cool to play with bits however. 

Another issue with the boards was that the GND, 5V, and 3.3V of the rpi were broken out on the board, meaning that if you just plugged things in at random you very quickly broke something. These pins would need to be trimmed on any board for beginners. I also didn’t have extra op-amps, which meant that I couldn’t give the students any other op amps if they broke thiers during soldering. No one appeared to mess with the logic chips or to combine multiple videos feeds together.

I learned from this workshop that it is very challenging to do a rpi zero workshop, the need for USB adaptors, power supplies that supply up to 3A, HDMI adapters, multiple screens, keyboards and mice, and a literacy in Linux all make it extremely ambitious and software oriented. It made me want to do this workshop entirely in hardware somehow.

IDEA : randomly generate different equations to make patterns with touch of button.

*****

Put three of the rpi boards together, check it out :

****

Some nice photography references :

Bea Nettles

Christian Schad

Weegee

Alvin Langdon

*****

Little experiment using the FPGA VGA simulator site https://8bitworkshop.com/v3.9.0/?platform=verilog-vga&file=test_hvsync.v : 

`include "hvsync_generator.v"

/*
A simple test pattern using the hvsync_generator module.
*/

module test_hvsync_top(clk, reset, hsync, vsync, rgb);

input clk, reset;
output hsync, vsync;
output [2:0] rgb;
wire display_on;
wire [9:0] hpos;
wire [9:0] vpos;

hvsync_generator hvsync_gen(
.clk(clk),
.reset(0),
.hsync(hsync),
.vsync(vsync),
.display_on(display_on),
.hpos(hpos),
.vpos(vpos)
);

reg [27:0] counter ;

always@(posedge clk) begin
counter <= counter + 1;
end


always@(*) begin
case(counter[27:22])
6'b000000: out_bit = bit_or;
6'b000001: out_bit = bit_xor;
6'b000010: out_bit = bit_and;
6'b000011: out_bit = bit_nand;
6'b000100: out_bit = bit_xnor;
6'b000101: out_bit = bit_or[9:0]& ~vpos[9:0];
6'b000110: out_bit = bit_xor[9:0]& ~vpos[9:0];
6'b000111: out_bit = bit_and[9:0]& ~vpos[9:0];
6'b001000: out_bit = bit_xnor[9:0]& ~vpos[9:0];
6'b001001: out_bit = hpos[9:0]& ~bit_or[9:0];
6'b001010: out_bit = hpos[9:0]& ~bit_xor[9:0];
6'b001011: out_bit = hpos[9:0]& ~bit_and[9:0];
6'b001100: out_bit = hpos[9:0]& ~bit_nand[9:0];
6'b001101: out_bit = hpos[9:0]& ~bit_xnor[9:0];
6'b001110: out_bit = bit_or[9:0]|vpos[9:0];
6'b001111: out_bit = bit_xor[9:0]|vpos[9:0];
6'b010000: out_bit = bit_and[9:0]|vpos[9:0];
6'b010001: out_bit = bit_nand[9:0]|vpos[9:0];
6'b010010: out_bit = bit_xnor[9:0]|vpos[9:0];
6'b010011: out_bit = hpos[9:0]|bit_or[9:0];
6'b010100: out_bit = hpos[9:0]|bit_xor[9:0];
6'b010101: out_bit = hpos[9:0]|bit_and[9:0];
6'b010110: out_bit = hpos[9:0]|bit_nand[9:0];
6'b010111: out_bit = hpos[9:0]|bit_xnor[9:0];
6'b011000: out_bit = bit_or[9:0]^vpos[9:0];
6'b011001: out_bit = bit_xor[9:0]^vpos[9:0];
6'b011010: out_bit = bit_and[9:0]^vpos[9:0];
6'b011011: out_bit = bit_nand[9:0]^vpos[9:0];
6'b011100: out_bit = bit_xnor[9:0]^vpos[9:0];
6'b011101: out_bit = hpos[9:0]^bit_or[9:0];
6'b011110: out_bit = hpos[9:0]^bit_xor[9:0];
6'b011111: out_bit = hpos[9:0]^bit_and[9:0];
6'b100000: out_bit = hpos[9:0]^bit_nand[9:0];
6'b100001: out_bit = hpos[9:0]^bit_xnor[9:0];
6'b100010: out_bit = bit_or[9:0]&vpos[9:0];
6'b100011: out_bit = bit_xor[9:0]&vpos[9:0];
6'b100100: out_bit = bit_and[9:0]&vpos[9:0];
6'b100101: out_bit = bit_nand[9:0]&vpos[9:0];
6'b100110: out_bit = bit_xnor[9:0]&vpos[9:0];
6'b100111: out_bit = hpos[9:0]&bit_or[9:0];
6'b101000: out_bit = hpos[9:0]&bit_xor[9:0];
6'b101001: out_bit = hpos[9:0]&bit_and[9:0];
6'b101010: out_bit = hpos[9:0]&bit_nand[9:0];
6'b101011: out_bit = hpos[9:0]&bit_xnor[9:0];
6'b101100: out_bit = bit_or[9:0]^ ~vpos[9:0];
6'b101101: out_bit = bit_xor[9:0]^ ~vpos[9:0];
6'b101110: out_bit = bit_and[9:0]^ ~vpos[9:0];
6'b101111: out_bit = bit_nand[9:0]^ ~vpos[9:0];
6'b110000: out_bit = bit_xnor[9:0]^ ~vpos[9:0];
6'b110001: out_bit = hpos[9:0]^ ~bit_or[9:0];
6'b110010: out_bit = hpos[9:0]^ ~bit_xor[9:0];
6'b110011: out_bit = hpos[9:0]^ ~bit_and[9:0];
6'b110100: out_bit = hpos[9:0]^ ~bit_nand[9:0];
6'b110101: out_bit = hpos[9:0]^ ~bit_xnor[9:0];
6'b110110: out_bit = bit_or[9:0]^ ~bit_xor[9:0];
6'b110111: out_bit = bit_or[9:0]^ ~bit_and[9:0];
6'b111000: out_bit = bit_or[9:0]^ ~bit_nand[9:0];
6'b111001: out_bit = bit_or[9:0]^ ~bit_xnor[9:0];
6'b111010: out_bit = bit_or[9:0]&bit_xor[9:0];
6'b111011: out_bit = bit_or[9:0]&bit_and[9:0];
6'b111100: out_bit = bit_or[9:0]&bit_nand[9:0];
6'b111101: out_bit = bit_or[9:0]&bit_xnor[9:0];
6'b111110: out_bit = bit_or[9:0]^bit_xor[9:0];
6'b111111: out_bit = bit_or[9:0]^bit_and[9:0];
default: out_bit = bit_xnor;
endcase

end

reg [9:0] out_bit ;

assign out_bit = bit_or[9:0]& ~vpos[9:0];

wire [9:0] bit_or;
assign bit_or = hpos[9:0]|vpos[9:0];

wire [9:0] bit_xor;
assign bit_xor = hpos[9:0]^vpos[9:0];

wire [9:0] bit_and;
assign bit_and = hpos[9:0]&vpos[9:0];

wire [9:0] bit_nand;
assign bit_nand = hpos[9:0]& ~vpos[9:0];

wire [9:0] bit_xnor;
assign bit_xnor = hpos[9:0]^ ~vpos[9:0];

wire r ;
wire g ;
wire b ;

assign r = (out_bit[9:0]>10'b0100000000) ? 1'b1 : 1'b0 ;
assign g = (out_bit[9:0]>10'b1000000000) ? 1'b1 : 1'b0 ;
assign b = (out_bit[9:0]>10'b0010000000) ? 1'b1 : 1'b0 ;


assign rgb = {b,g,r};

endmodule

playing with these values gives all kinds of pretty forms : 

assign r = (out_bit[9:0]>10'b0100000000) ? 1'b1 : 1'b0 ;

assign g = (out_bit[9:0]>10'b1000000000) ? 1'b1 : 1'b0 ;

assign b = (out_bit[9:0]>10'b0010000000) ? 1'b1 : 1'b0 ;

*********

Back trying to make a board to mess with the OV7670.

So far this is the only code that appears to work with Arduino :

#include <stdint.h>
#include <avr/io.h>
#include <util/twi.h>
#include <util/delay.h>
#include <avr/pgmspace.h>
#define F_CPU 16000000UL
#define vga   0
#define qvga  1
#define qqvga   2
#define yuv422  0
#define rgb565  1
#define bayerRGB  2
#define camAddr_WR  0x42
#define camAddr_RD  0x43
/* Registers */
#define REG_GAIN    0x00  /* Gain lower 8 bits (rest in vref) */
#define REG_BLUE    0x01  /* blue gain */
#define REG_RED       0x02  /* red gain */
#define REG_VREF    0x03  /* Pieces of GAIN, VSTART, VSTOP */
#define REG_COM1    0x04  /* Control 1 */
#define COM1_CCIR656  0x40    /* CCIR656 enable */
#define REG_BAVE    0x05  /* U/B Average level */
#define REG_GbAVE   0x06  /* Y/Gb Average level */
#define REG_AECHH   0x07  /* AEC MS 5 bits */
#define REG_RAVE    0x08  /* V/R Average level */
#define REG_COM2    0x09  /* Control 2 */
#define COM2_SSLEEP         0x10  /* Soft sleep mode */
#define REG_PID           0x0a  /* Product ID MSB */
#define REG_VER           0x0b  /* Product ID LSB */
#define REG_COM3    0x0c  /* Control 3 */
#define COM3_SWAP         0x40  /* Byte swap */
#define COM3_SCALEEN          0x08  /* Enable scaling */
#define COM3_DCWEN          0x04  /* Enable downsamp/crop/window */
#define REG_COM4    0x0d  /* Control 4 */
#define REG_COM5    0x0e  /* All "reserved" */
#define REG_COM6    0x0f  /* Control 6 */
#define REG_AECH    0x10  /* More bits of AEC value */
#define REG_CLKRC   0x11  /* Clocl control */
#define CLK_EXT           0x40  /* Use external clock directly */
#define CLK_SCALE   0x3f  /* Mask for internal clock scale */
#define REG_COM7    0x12  /* Control 7 */ //REG mean address.
#define COM7_RESET          0x80  /* Register reset */
#define COM7_FMT_MASK         0x38
#define COM7_FMT_VGA          0x00
#define COM7_FMT_CIF          0x20  /* CIF format */
#define COM7_FMT_QVGA         0x10  /* QVGA format */
#define COM7_FMT_QCIF         0x08  /* QCIF format */
#define COM7_RGB          0x04  /* bits 0 and 2 - RGB format */
#define COM7_YUV          0x00  /* YUV */
#define COM7_BAYER          0x01  /* Bayer format */
#define COM7_PBAYER         0x05  /* "Processed bayer" */
#define REG_COM8    0x13  /* Control 8 */
#define COM8_FASTAEC          0x80  /* Enable fast AGC/AEC */
#define COM8_AECSTEP          0x40  /* Unlimited AEC step size */
#define COM8_BFILT    0x20  /* Band filter enable */
#define COM8_AGC    0x04  /* Auto gain enable */
#define COM8_AWB    0x02  /* White balance enable */
#define COM8_AEC    0x01  /* Auto exposure enable */
#define REG_COM9    0x14  /* Control 9- gain ceiling */
#define REG_COM10   0x15  /* Control 10 */
#define COM10_HSYNC         0x40  /* HSYNC instead of HREF */
#define COM10_PCLK_HB         0x20  /* Suppress PCLK on horiz blank */
#define COM10_HREF_REV          0x08  /* Reverse HREF */
#define COM10_VS_LEAD         0x04  /* VSYNC on clock leading edge */
#define COM10_VS_NEG          0x02  /* VSYNC negative */
#define COM10_HS_NEG          0x01  /* HSYNC negative */
#define REG_HSTART    0x17  /* Horiz start high bits */
#define REG_HSTOP   0x18  /* Horiz stop high bits */
#define REG_VSTART    0x19  /* Vert start high bits */
#define REG_VSTOP   0x1a  /* Vert stop high bits */
#define REG_PSHFT   0x1b  /* Pixel delay after HREF */
#define REG_MIDH    0x1c  /* Manuf. ID high */
#define REG_MIDL    0x1d  /* Manuf. ID low */
#define REG_MVFP    0x1e  /* Mirror / vflip */
#define MVFP_MIRROR         0x20  /* Mirror image */
#define MVFP_FLIP   0x10  /* Vertical flip */
#define REG_AEW           0x24  /* AGC upper limit */
#define REG_AEB           0x25    /* AGC lower limit */
#define REG_VPT           0x26  /* AGC/AEC fast mode op region */
#define REG_HSYST   0x30  /* HSYNC rising edge delay */
#define REG_HSYEN   0x31  /* HSYNC falling edge delay */
#define REG_HREF    0x32  /* HREF pieces */
#define REG_TSLB    0x3a  /* lots of stuff */
#define TSLB_YLAST    0x04  /* UYVY or VYUY - see com13 */
#define REG_COM11   0x3b  /* Control 11 */
#define COM11_NIGHT         0x80  /* NIght mode enable */
#define COM11_NMFR          0x60  /* Two bit NM frame rate */
#define COM11_HZAUTO          0x10  /* Auto detect 50/60 Hz */
#define COM11_50HZ          0x08  /* Manual 50Hz select */
#define COM11_EXP   0x02
#define REG_COM12   0x3c  /* Control 12 */
#define COM12_HREF          0x80  /* HREF always */
#define REG_COM13   0x3d  /* Control 13 */
#define COM13_GAMMA         0x80  /* Gamma enable */
#define COM13_UVSAT         0x40  /* UV saturation auto adjustment */
#define COM13_UVSWAP          0x01  /* V before U - w/TSLB */
#define REG_COM14   0x3e  /* Control 14 */
#define COM14_DCWEN         0x10  /* DCW/PCLK-scale enable */
#define REG_EDGE    0x3f  /* Edge enhancement factor */
#define REG_COM15   0x40  /* Control 15 */
#define COM15_R10F0         0x00  /* Data range 10 to F0 */
#define COM15_R01FE         0x80  /*      01 to FE */
#define COM15_R00FF         0xc0  /*      00 to FF */
#define COM15_RGB565          0x10  /* RGB565 output */
#define COM15_RGB555          0x30  /* RGB555 output */
#define REG_COM16   0x41  /* Control 16 */
#define COM16_AWBGAIN         0x08  /* AWB gain enable */
#define REG_COM17   0x42  /* Control 17 */
#define COM17_AECWIN          0xc0  /* AEC window - must match COM4 */
#define COM17_CBAR          0x08  /* DSP Color bar */
/*
* This matrix defines how the colors are generated, must be
* tweaked to adjust hue and saturation.
*
* Order: v-red, v-green, v-blue, u-red, u-green, u-blue
* They are nine-bit signed quantities, with the sign bit
* stored in0x58.Sign for v-red is bit 0, and up from there.
*/
#define REG_CMATRIX_BASE  0x4f
#define CMATRIX_LEN           6
#define REG_CMATRIX_SIGN  0x58
#define REG_BRIGHT    0x55  /* Brightness */
#define REG_CONTRAS         0x56  /* Contrast control */
#define REG_GFIX    0x69  /* Fix gain control */
#define REG_REG76   0x76  /* OV's name */
#define R76_BLKPCOR         0x80  /* Black pixel correction enable */
#define R76_WHTPCOR         0x40  /* White pixel correction enable */
#define REG_RGB444          0x8c  /* RGB 444 control */
#define R444_ENABLE         0x02  /* Turn on RGB444, overrides 5x5 */
#define R444_RGBX   0x01  /* Empty nibble at end */
#define REG_HAECC1    0x9f  /* Hist AEC/AGC control 1 */
#define REG_HAECC2    0xa0  /* Hist AEC/AGC control 2 */
#define REG_BD50MAX         0xa5  /* 50hz banding step limit */
#define REG_HAECC3    0xa6  /* Hist AEC/AGC control 3 */
#define REG_HAECC4    0xa7  /* Hist AEC/AGC control 4 */
#define REG_HAECC5    0xa8  /* Hist AEC/AGC control 5 */
#define REG_HAECC6    0xa9  /* Hist AEC/AGC control 6 */
#define REG_HAECC7    0xaa  /* Hist AEC/AGC control 7 */
#define REG_BD60MAX         0xab  /* 60hz banding step limit */
#define REG_GAIN    0x00  /* Gain lower 8 bits (rest in vref) */
#define REG_BLUE    0x01  /* blue gain */
#define REG_RED           0x02  /* red gain */
#define REG_VREF    0x03  /* Pieces of GAIN, VSTART, VSTOP */
#define REG_COM1    0x04  /* Control 1 */
#define COM1_CCIR656          0x40  /* CCIR656 enable */
#define REG_BAVE    0x05  /* U/B Average level */
#define REG_GbAVE   0x06  /* Y/Gb Average level */
#define REG_AECHH   0x07  /* AEC MS 5 bits */
#define REG_RAVE    0x08  /* V/R Average level */
#define REG_COM2    0x09  /* Control 2 */
#define COM2_SSLEEP         0x10  /* Soft sleep mode */
#define REG_PID           0x0a  /* Product ID MSB */
#define REG_VER           0x0b  /* Product ID LSB */
#define REG_COM3    0x0c  /* Control 3 */
#define COM3_SWAP         0x40  /* Byte swap */
#define COM3_SCALEEN          0x08  /* Enable scaling */
#define COM3_DCWEN          0x04  /* Enable downsamp/crop/window */
#define REG_COM4    0x0d  /* Control 4 */
#define REG_COM5    0x0e  /* All "reserved" */
#define REG_COM6    0x0f  /* Control 6 */
#define REG_AECH    0x10  /* More bits of AEC value */
#define REG_CLKRC   0x11  /* Clocl control */
#define CLK_EXT           0x40  /* Use external clock directly */
#define CLK_SCALE   0x3f  /* Mask for internal clock scale */
#define REG_COM7    0x12  /* Control 7 */
#define COM7_RESET          0x80  /* Register reset */
#define COM7_FMT_MASK         0x38
#define COM7_FMT_VGA          0x00
#define COM7_FMT_CIF          0x20  /* CIF format */
#define COM7_FMT_QVGA         0x10  /* QVGA format */
#define COM7_FMT_QCIF         0x08  /* QCIF format */
#define COM7_RGB    0x04  /* bits 0 and 2 - RGB format */
#define COM7_YUV    0x00  /* YUV */
#define COM7_BAYER          0x01  /* Bayer format */
#define COM7_PBAYER         0x05  /* "Processed bayer" */
#define REG_COM8    0x13  /* Control 8 */
#define COM8_FASTAEC          0x80  /* Enable fast AGC/AEC */
#define COM8_AECSTEP          0x40  /* Unlimited AEC step size */
#define COM8_BFILT    0x20  /* Band filter enable */
#define COM8_AGC    0x04  /* Auto gain enable */
#define COM8_AWB    0x02  /* White balance enable */
#define COM8_AEC    0x01  /* Auto exposure enable */
#define REG_COM9    0x14  /* Control 9- gain ceiling */
#define REG_COM10   0x15  /* Control 10 */
#define COM10_HSYNC         0x40  /* HSYNC instead of HREF */
#define COM10_PCLK_HB         0x20  /* Suppress PCLK on horiz blank */
#define COM10_HREF_REV          0x08  /* Reverse HREF */
#define COM10_VS_LEAD           0x04  /* VSYNC on clock leading edge */
#define COM10_VS_NEG          0x02  /* VSYNC negative */
#define COM10_HS_NEG          0x01  /* HSYNC negative */
#define REG_HSTART    0x17  /* Horiz start high bits */
#define REG_HSTOP   0x18  /* Horiz stop high bits */
#define REG_VSTART    0x19  /* Vert start high bits */
#define REG_VSTOP   0x1a  /* Vert stop high bits */
#define REG_PSHFT   0x1b  /* Pixel delay after HREF */
#define REG_MIDH    0x1c  /* Manuf. ID high */
#define REG_MIDL    0x1d  /* Manuf. ID low */
#define REG_MVFP    0x1e  /* Mirror / vflip */
#define MVFP_MIRROR         0x20  /* Mirror image */
#define MVFP_FLIP   0x10  /* Vertical flip */
#define REG_AEW           0x24  /* AGC upper limit */
#define REG_AEB           0x25  /* AGC lower limit */
#define REG_VPT           0x26  /* AGC/AEC fast mode op region */
#define REG_HSYST   0x30  /* HSYNC rising edge delay */
#define REG_HSYEN   0x31  /* HSYNC falling edge delay */
#define REG_HREF    0x32  /* HREF pieces */
#define REG_TSLB    0x3a  /* lots of stuff */
#define TSLB_YLAST    0x04  /* UYVY or VYUY - see com13 */
#define REG_COM11   0x3b  /* Control 11 */
#define COM11_NIGHT         0x80  /* NIght mode enable */
#define COM11_NMFR          0x60  /* Two bit NM frame rate */
#define COM11_HZAUTO          0x10  /* Auto detect 50/60 Hz */
#define COM11_50HZ          0x08  /* Manual 50Hz select */
#define COM11_EXP   0x02
#define REG_COM12   0x3c  /* Control 12 */
#define COM12_HREF          0x80  /* HREF always */
#define REG_COM13   0x3d  /* Control 13 */
#define COM13_GAMMA         0x80  /* Gamma enable */
#define COM13_UVSAT         0x40  /* UV saturation auto adjustment */
#define COM13_UVSWAP          0x01  /* V before U - w/TSLB */
#define REG_COM14   0x3e  /* Control 14 */
#define COM14_DCWEN         0x10  /* DCW/PCLK-scale enable */
#define REG_EDGE    0x3f  /* Edge enhancement factor */
#define REG_COM15   0x40  /* Control 15 */
#define COM15_R10F0         0x00  /* Data range 10 to F0 */
#define COM15_R01FE         0x80  /*      01 to FE */
#define COM15_R00FF         0xc0  /*      00 to FF */
#define COM15_RGB565          0x10  /* RGB565 output */
#define COM15_RGB555          0x30  /* RGB555 output */
#define REG_COM16   0x41  /* Control 16 */
#define COM16_AWBGAIN         0x08  /* AWB gain enable */
#define REG_COM17   0x42  /* Control 17 */
#define COM17_AECWIN          0xc0  /* AEC window - must match COM4 */
#define COM17_CBAR          0x08  /* DSP Color bar */
#define CMATRIX_LEN             6
#define REG_BRIGHT    0x55  /* Brightness */
#define REG_REG76   0x76  /* OV's name */
#define R76_BLKPCOR         0x80  /* Black pixel correction enable */
#define R76_WHTPCOR         0x40  /* White pixel correction enable */
#define REG_RGB444          0x8c  /* RGB 444 control */
#define R444_ENABLE         0x02  /* Turn on RGB444, overrides 5x5 */
#define R444_RGBX   0x01  /* Empty nibble at end */
#define REG_HAECC1    0x9f  /* Hist AEC/AGC control 1 */
#define REG_HAECC2    0xa0  /* Hist AEC/AGC control 2 */
#define REG_BD50MAX         0xa5  /* 50hz banding step limit */
#define REG_HAECC3    0xa6  /* Hist AEC/AGC control 3 */
#define REG_HAECC4    0xa7  /* Hist AEC/AGC control 4 */
#define REG_HAECC5    0xa8  /* Hist AEC/AGC control 5 */
#define REG_HAECC6    0xa9  /* Hist AEC/AGC control 6 */
#define REG_HAECC7    0xaa  /* Hist AEC/AGC control 7 */
#define REG_BD60MAX         0xab  /* 60hz banding step limit */
#define MTX1            0x4f  /* Matrix Coefficient 1 */
#define MTX2            0x50  /* Matrix Coefficient 2 */
#define MTX3            0x51  /* Matrix Coefficient 3 */
#define MTX4            0x52  /* Matrix Coefficient 4 */
#define MTX5            0x53  /* Matrix Coefficient 5 */
#define MTX6            0x54  /* Matrix Coefficient 6 */
#define REG_CONTRAS         0x56  /* Contrast control */
#define MTXS            0x58  /* Matrix Coefficient Sign */
#define AWBC7           0x59  /* AWB Control 7 */
#define AWBC8           0x5a  /* AWB Control 8 */
#define AWBC9           0x5b  /* AWB Control 9 */
#define AWBC10            0x5c  /* AWB Control 10 */
#define AWBC11            0x5d  /* AWB Control 11 */
#define AWBC12            0x5e  /* AWB Control 12 */
#define REG_GFI           0x69  /* Fix gain control */
#define GGAIN           0x6a  /* G Channel AWB Gain */
#define DBLV            0x6b  
#define AWBCTR3           0x6c  /* AWB Control 3 */
#define AWBCTR2           0x6d  /* AWB Control 2 */
#define AWBCTR1           0x6e  /* AWB Control 1 */
#define AWBCTR0           0x6f  /* AWB Control 0 */
struct regval_list{
  uint8_t reg_num;
  uint16_t value;
};
const struct regval_list qvga_ov7670[] PROGMEM = {
  { REG_HSTART, 0x16 },
  { REG_HSTOP, 0x04 },
  { REG_HREF, 0xa4 },
  { REG_VSTART, 0x02 },
  { REG_VSTOP, 0x7a },
  { REG_VREF, 0x0a },
  { 0xff, 0xff }, /* END MARKER */
};
const struct regval_list yuv422_ov7670[] PROGMEM = {
  { REG_COM9, 0x6A }, /* 128x gain ceiling; 0x8 is reserved bit */
  { 0x4f, 0x80 },   /* "matrix coefficient 1" */
  { 0x50, 0x80 },   /* "matrix coefficient 2" */
  { 0x51, 0 },    /* vb */
  { 0x52, 0x22 },   /* "matrix coefficient 4" */
  { 0x53, 0x5e },   /* "matrix coefficient 5" */
  { 0x54, 0x80 },   /* "matrix coefficient 6" */
  { REG_COM13, COM13_UVSAT },
  { 0xff, 0xff },   /* END MARKER */
};
const struct regval_list ov7670_default_regs[] PROGMEM = {//from the linux driver
  { REG_COM7, COM7_RESET },
  { REG_TSLB, 0x04 }, /* OV */
  { REG_COM7, 0 },  /* VGA */
  /*
  * Set the hardware window.  These values from OV don't entirely
  * make sense - hstop is less than hstart.  But they work...
  */
  { REG_HSTART, 0x13 }, { REG_HSTOP, 0x01 },
  { REG_HREF, 0xb6 }, { REG_VSTART, 0x02 },
  { REG_VSTOP, 0x7a }, { REG_VREF, 0x0a },
  { REG_COM3, 0 }, { REG_COM14, 0 },
  /* Mystery scaling numbers */
  { 0x70, 0x3a }, { 0x71, 0x35 },
  { 0x72, 0x11 }, { 0x73, 0xf0 },
  { 0xa2,/* 0x02 changed to 1*/1 }, { REG_COM10, 0x0 },
  /* Gamma curve values */
  { 0x7a, 0x20 }, { 0x7b, 0x10 },
  { 0x7c, 0x1e }, { 0x7d, 0x35 },
  { 0x7e, 0x5a }, { 0x7f, 0x69 },
  { 0x80, 0x76 }, { 0x81, 0x80 },
  { 0x82, 0x88 }, { 0x83, 0x8f },
  { 0x84, 0x96 }, { 0x85, 0xa3 },
  { 0x86, 0xaf }, { 0x87, 0xc4 },
  { 0x88, 0xd7 }, { 0x89, 0xe8 },
  /* AGC and AEC parameters.  Note we start by disabling those features,
  then turn them only after tweaking the values. */
  { REG_COM8, COM8_FASTAEC | COM8_AECSTEP },
  { REG_GAIN, 0 }, { REG_AECH, 0 },
  { REG_COM4, 0x40 }, /* magic reserved bit */
  { REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */
  { REG_BD50MAX, 0x05 }, { REG_BD60MAX, 0x07 },
  { REG_AEW, 0x95 }, { REG_AEB, 0x33 },
  { REG_VPT, 0xe3 }, { REG_HAECC1, 0x78 },
  { REG_HAECC2, 0x68 }, { 0xa1, 0x03 }, /* magic */
  { REG_HAECC3, 0xd8 }, { REG_HAECC4, 0xd8 },
  { REG_HAECC5, 0xf0 }, { REG_HAECC6, 0x90 },
  { REG_HAECC7, 0x94 },
  { REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_AGC | COM8_AEC },
  { 0x30, 0 }, { 0x31, 0 },//disable some delays
  /* Almost all of these are magic "reserved" values.  */
  { REG_COM5, 0x61 }, { REG_COM6, 0x4b },
  { 0x16, 0x02 }, { REG_MVFP, 0x07 },
  { 0x21, 0x02 }, { 0x22, 0x91 },
  { 0x29, 0x07 }, { 0x33, 0x0b },
  { 0x35, 0x0b }, { 0x37, 0x1d },
  { 0x38, 0x71 }, { 0x39, 0x2a },
  { REG_COM12, 0x78 }, { 0x4d, 0x40 },
  { 0x4e, 0x20 }, { REG_GFIX, 0 },
  /*{0x6b, 0x4a},*/{ 0x74, 0x10 },
  { 0x8d, 0x4f }, { 0x8e, 0 },
  { 0x8f, 0 }, { 0x90, 0 },
  { 0x91, 0 }, { 0x96, 0 },
  { 0x9a, 0 }, { 0xb0, 0x84 },
  { 0xb1, 0x0c }, { 0xb2, 0x0e },
  { 0xb3, 0x82 }, { 0xb8, 0x0a },
  /* More reserved magic, some of which tweaks white balance */
  { 0x43, 0x0a }, { 0x44, 0xf0 },
  { 0x45, 0x34 }, { 0x46, 0x58 },
  { 0x47, 0x28 }, { 0x48, 0x3a },
  { 0x59, 0x88 }, { 0x5a, 0x88 },
  { 0x5b, 0x44 }, { 0x5c, 0x67 },
  { 0x5d, 0x49 }, { 0x5e, 0x0e },
  { 0x6c, 0x0a }, { 0x6d, 0x55 },
  { 0x6e, 0x11 }, { 0x6f, 0x9e }, /* it was 0x9F "9e for advance AWB" */
  { 0x6a, 0x40 }, { REG_BLUE, 0x40 },
  { REG_RED, 0x60 },
  { REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_AGC | COM8_AEC | COM8_AWB },
  /* Matrix coefficients */
  { 0x4f, 0x80 }, { 0x50, 0x80 },
  { 0x51, 0 },    { 0x52, 0x22 },
  { 0x53, 0x5e }, { 0x54, 0x80 },
  { 0x58, 0x9e },
  { REG_COM16, COM16_AWBGAIN }, { REG_EDGE, 0 },
  { 0x75, 0x05 }, { REG_REG76, 0xe1 },
  { 0x4c, 0 },     { 0x77, 0x01 },
  { REG_COM13, /*0xc3*/0x48 }, { 0x4b, 0x09 },
  { 0xc9, 0x60 },   /*{REG_COM16, 0x38},*/
  { 0x56, 0x40 },
  { 0x34, 0x11 }, { REG_COM11, COM11_EXP | COM11_HZAUTO },
  { 0xa4, 0x82/*Was 0x88*/ }, { 0x96, 0 },
  { 0x97, 0x30 }, { 0x98, 0x20 },
  { 0x99, 0x30 }, { 0x9a, 0x84 },
  { 0x9b, 0x29 }, { 0x9c, 0x03 },
  { 0x9d, 0x4c }, { 0x9e, 0x3f },
  { 0x78, 0x04 },
  /* Extra-weird stuff.  Some sort of multiplexor register */
  { 0x79, 0x01 }, { 0xc8, 0xf0 },
  { 0x79, 0x0f }, { 0xc8, 0x00 },
  { 0x79, 0x10 }, { 0xc8, 0x7e },
  { 0x79, 0x0a }, { 0xc8, 0x80 },
  { 0x79, 0x0b }, { 0xc8, 0x01 },
  { 0x79, 0x0c }, { 0xc8, 0x0f },
  { 0x79, 0x0d }, { 0xc8, 0x20 },
  { 0x79, 0x09 }, { 0xc8, 0x80 },
  { 0x79, 0x02 }, { 0xc8, 0xc0 },
  { 0x79, 0x03 }, { 0xc8, 0x40 },
  { 0x79, 0x05 }, { 0xc8, 0x30 },
  { 0x79, 0x26 },
  { 0xff, 0xff }, /* END MARKER */
};
void error_led(void){
  DDRB |= 32;//make sure led is output
  while (1){//wait for reset
    PORTB ^= 32;// toggle led
    _delay_ms(100);
  }
}
void twiStart(void){
  TWCR = _BV(TWINT) | _BV(TWSTA) | _BV(TWEN);//send start
  while (!(TWCR & (1 << TWINT)));//wait for start to be transmitted
  if ((TWSR & 0xF8) != TW_START)
    error_led();
}
void twiWriteByte(uint8_t DATA, uint8_t type){
  TWDR = DATA;
  TWCR = _BV(TWINT) | _BV(TWEN);
  while (!(TWCR & (1 << TWINT))) {}
  if ((TWSR & 0xF8) != type)
    error_led();
}
void twiAddr(uint8_t addr, uint8_t typeTWI){
  TWDR = addr;//send address
  TWCR = _BV(TWINT) | _BV(TWEN);    /* clear interrupt to start transmission */
  while ((TWCR & _BV(TWINT)) == 0); /* wait for transmission */
  if ((TWSR & 0xF8) != typeTWI)
    error_led();
}
void writeReg(uint8_t reg, uint8_t dat){
  //send start condition
  twiStart();
  twiAddr(camAddr_WR, TW_MT_SLA_ACK);
  twiWriteByte(reg, TW_MT_DATA_ACK);
  twiWriteByte(dat, TW_MT_DATA_ACK);
  TWCR = (1 << TWINT) | (1 << TWEN) | (1 << TWSTO);//send stop
  _delay_ms(1);
}
static uint8_t twiRd(uint8_t nack){
  if (nack){
    TWCR = _BV(TWINT) | _BV(TWEN);
    while ((TWCR & _BV(TWINT)) == 0); /* wait for transmission */
    if ((TWSR & 0xF8) != TW_MR_DATA_NACK)
      error_led();
    return TWDR;
  }
  else{
    TWCR = _BV(TWINT) | _BV(TWEN) | _BV(TWEA);
    while ((TWCR & _BV(TWINT)) == 0); /* wait for transmission */
    if ((TWSR & 0xF8) != TW_MR_DATA_ACK)
      error_led();
    return TWDR;
  }
}
uint8_t rdReg(uint8_t reg){
  uint8_t dat;
  twiStart();
  twiAddr(camAddr_WR, TW_MT_SLA_ACK);
  twiWriteByte(reg, TW_MT_DATA_ACK);
  TWCR = (1 << TWINT) | (1 << TWEN) | (1 << TWSTO);//send stop
  _delay_ms(1);
  twiStart();
  twiAddr(camAddr_RD, TW_MR_SLA_ACK);
  dat = twiRd(1);
  TWCR = (1 << TWINT) | (1 << TWEN) | (1 << TWSTO);//send stop
  _delay_ms(1);
  return dat;
}
void wrSensorRegs8_8(const struct regval_list reglist[]){
  uint8_t reg_addr, reg_val;
  const struct regval_list *next = reglist;
  while ((reg_addr != 0xff) | (reg_val != 0xff)){
    reg_addr = pgm_read_byte(&next->reg_num);
    reg_val = pgm_read_byte(&next->value);
   writeReg(reg_addr, reg_val);
    next++;
  }
}
void setColor(void){
  //wrSensorRegs8_8(yuv422_ov7670);
  wrSensorRegs8_8(qvga_ov7670);
}
void setResolution(void){
 writeReg(REG_COM3, 4); // REG_COM3 enable scaling
  wrSensorRegs8_8(qvga_ov7670);
}
void camInit(void){
 writeReg(0x12, 0x80);
  _delay_ms(100);
  wrSensorRegs8_8(ov7670_default_regs);
 writeReg(REG_COM10, 32);//PCLK does not toggle on HBLANK.
}
void arduinoUnoInut(void) {
  cli();//disable interrupts
    /* Setup the 8mhz PWM clock
  * This will be on pin 11*/
  DDRB |= (1 << 3);//pin 11
  ASSR &= ~(_BV(EXCLK) | _BV(AS2));
  TCCR2A = (1 << COM2A0) | (1 << WGM21) | (1 << WGM20);
  TCCR2B = (1 << WGM22) | (1 << CS20);
  OCR2A = 1;//(F_CPU)/(2*(X+1))
  DDRC &= ~15;//low d0-d3 camera
  DDRD &= ~252;//d7-d4 and interrupt pins
  _delay_ms(3000);
    //set up twi for 100khz
  TWSR &= ~3;//disable prescaler for TWI
  TWBR = 72;//set to 100khz
    //enable serial
  UBRR0H = 0;
  UBRR0L = 7;//0 = 2M baud rate. 1 = 1M baud. 3 = 0.5M. 7 = 250k 207 is 9600 baud rate.
  UCSR0A |= 2;//double speed aysnc
  UCSR0B = (1 << RXEN0) | (1 << TXEN0);//Enable receiver and transmitter
  UCSR0C = 6;//async 1 stop bit 8bit char no parity bits
}
void StringPgm(const char * str){
  do{
      while (!(UCSR0A & (1 << UDRE0)));//wait for byte to transmit
      UDR0 = pgm_read_byte_near(str);
      while (!(UCSR0A & (1 << UDRE0)));//wait for byte to transmit
  } while (pgm_read_byte_near(++str));
}
static void captureImg(uint16_t wg, uint16_t hg){
  uint16_t y, x;
  StringPgm(PSTR("*RDY*"));
  while (!(PIND & 8));//wait for high
  while ((PIND & 8));//wait for low
    y = hg;
  while (y--){
        x = wg;
      //while (!(PIND & 256));//wait for high
    while (x--){
      while ((PIND & 4));//wait for low
            UDR0 = (PINC & 15) | (PIND & 240);
          while (!(UCSR0A & (1 << UDRE0)));//wait for byte to transmit
      while (!(PIND & 4));//wait for high
      while ((PIND & 4));//wait for low
      while (!(PIND & 4));//wait for high
    }
    //  while ((PIND & 256));//wait for low
  }
    _delay_ms(100);
}
void setup(){
  arduinoUnoInut();
  camInit();
  setResolution();
  setColor();
 writeReg(0x11, 10); //Earlier it had the value:writeReg(0x11, 12); New version works better for me :) !!!!
}
void loop(){
 // captureImg(320, 240);
}

Now I want to take the HSYNC, VSYNC, Pixel Clock, and 8 bit color info in with an FPGA.

Errata : 

• The OV7670 sends data in 8 bit parallel, it needs two bytes to send color data in RGB565 format. This means that for the color data of a single pixel there are two pixel clock transitions.
• Only some pins of the FPGA can be used for clock input, use a global buffer input for Pixel Clock.
• It appears to be OK to overlock the MCLK of the OV7670 to 25MHz.

********

Some FPGA FIR resources : 

https://www.fpga4student.com/2016/11/image-processing-on-fpga-verilog.html

https://www.dspguide.com/ch6/3.htm

https://www.hackster.io/whitney-knitter/dsp-for-fpga-simple-fir-filter-in-verilog-91208d

https://github.com/samiyaalizaidi/FIR-Filter

On DSP more generally :

https://www.analog.com/en/resources/technical-books/scientist_engineers_guide.html

https://visionbook.mit.edu/

On the rpi camera :

https://picamera.readthedocs.io/en/release-1.13/api_camera.html

****

Here’s the FIR filter output using samiya alizaidi’s code lightly modified (to take in only 2 bits and output 3 bits) :

Next step is to be able to turn it on and off with a button to see the effect better, and to have a potentiometer (or even a new board with a bunch of bots) to vary the taps live somehow.

****

I want to convolute in place an image recorded in BRAM. This will be a combination of down sampling and convoluting in parallel.

*****

MIT class using the OV7670 camera and an iCE40 :

https://github.com/westonb/OV7670-Verilog

Another MIT class which has a microchip to initialize the camera !

https://fpga.mit.edu/6205/F22/documentation/camera_board

The camera’s datasheet :

https://web.mit.edu/6.111/www/f2016/tools/OV7670_2006.pdf

Sobel filter implementation :

https://www.cs.columbia.edu/~sedwards/classes/2022/4840-spring/reports/CameraControl-report.pdf

opening up the rpi camera and trying different lenses (search it in google and you’ll find it).

Just a reminder, try to make stuff that is pretty that people will enjoy, not just stuff that is meaningful to me. It makes life so much easier.

Also, I have chosen to learn teaching, not being an artist. I like that teaching renders a service, and has a social dimension. It uses more of my skill sets, is more useful for employment, and has less silliness. 

***

Looking at the CVI documentation, (http://cmi.steverance.com/fairlight_docs/CVI_User_Manual.pdf) some great slides showing effects :

They all rely on having a screen buffer, where images taken from the live feed or sprites can be placed, and being able to mix (AND, OR, XOR, chroma keyed, analog mixed, etc.) that with live video. Predefined animations (shapes, random colors, gradients) can be added to these, and live video can also be filtered (pixelated, colorized, inverted, etc.).

One thing here I haven’t tested at all is recording an image and then recording another and creating a trail, for instance, what they appear to be calling Catch-Up, Doppelganger, and Trailing.

Now that I can store an image in memory, I could go back through it and modify it. I could invert, mirror, highlight edges, or do what they call a Checkerboard Slide shatter etc.

*******

Recording multiple images to overlay is difficult without a memory that has a write mask (as in case of BRAM) or byte enable pins on an SRAM, or having several seperate SRAMs. With the FPGA I’ve tried to quickly read the SRAM, store its contents, XOR with what I want to write, and then write that back, but haven’t had any success.

BRAMs with mask only apply to the 256×16 configuration. I can have 16 of these, but it means a only 4,096 pixels for the whole screen. Or a 64×64 pixel image like this :

Dual port SRAMs are small and very expensive, not sure there are useful for the project.

I could store four parallel images in the same memory space with these SRAMs which have four byte enable signals. Beware the High Byte and Low Byte enable pins from smaller SRAMs, it just toggles between two banks of I/O and doesn’t appear to do anything else. 

GSI : https://www.mouser.fr/datasheet/2/771/840183236CGT-976441.pdf

Alliance : https://www.mouser.fr/datasheet/2/12/AS8C803625_801825-1288399.pdf

Rensas : https://www.mouser.fr/datasheet/2/698/REN_71V25761_DST_20200727-1995952.pdf

******

I am now imagining a new board which would have the following elements :

• INPUT
  • Two video inputs with ESP32 and SD card : https://www.instructables.com/Play-Video-With-ESP32/
  • delay lines
  • select either comparator, amp, or individual bits
• A single SRAM which with four byte enable signals

*****

Cool box pixellation effect from https://kevinkripper.com/vsynth :

****

Some nice industrial design from a book about analogue interfaces :

****

Here’s the final version of the board :

The last minute changes involved mostly taking into account the 2.5V IO voltage of the FPGA and the memory. I had very few IOs to work with and had to take away some keys. I realized that this whole time I’ve been sending VSYNC and HSYNC VGA signals at 3.3V logic levels. I wonder if this will fix the stuttering or the screen turning off. I’ve added a shunt to power the rpi with or without the same supply as the board. I’m excited to try having the connectors on the bottom of the board, and putting everything inside the slanted 3D print. I’m tired of having the rpi cables disconnecting all the time.

******

I randomly picked up a book of Luis Buñuel’s surrealist work and found inspiring collages from Dali, Maurice Heine :

****

I went to the Cité des Sciences & Industrie, discovered the Aerofiat project where a designermade aerodynamic versions of the Fiat.

There were great expos related to sound, there was a delay tube showing that sound travels at around 360m/second and a bell rung in a vacuum that went silent, a frequency time plot of sound, and an open piano where you could whistle and the strings that were at that resonant frequency would keep vibrating back at you. There was a propogation demo, showing the fact that sound travels in compression and expansion zones.

And then the museum of music, where there was beautiful live music and a bunch of strange looking and exquisite instruments :

There was a little expo on Pierre Henry, the musique concrete composer. He treated old recordings like raw materials (samples) that he changed the speed of, added echos, reverbs, superposed tracks. One song was all composed from a single rusty door. I guess that could be a cool workshop activity, to ask students to remix a film. 

There was a nice looking synth he had where the flow diagram and different sub systems were drawn on the interface of the machine. I want to do the same thing with a PCB for the sound recorder for the Beaux Arts !

*****

The byte selectable SRAM appears to be working 🙂

Main error from the first version of the board :

• The rpi was upside down, I had to solder 40 female pins on the underside.
• The level shifter before the VGA out which was causing the video to not be legit. I desoldered it and jumped the inputs and outputs.
• The color select pin shunt is too close to the buttons.

I was worried about getting the SRAM working after pouring over the datasheet :

But in the end, it really comes down to ADSP toggling out of phase with the CLK while WE is either HIGH or LOW.

I soldered the solder bridge to power the board with a 5V 3A rpi power supply and so far so good.

Still some things to fix :

• DONE : Try recording perfectly square on the screen using:

  address = (h_count>>1)+((v_count>>1)*200);

• DONE : Some colors less visible, they should probably each be a mix of RGB.
• DONE : Some channels rarely catch the visible screen, I could use rpi_DEN to fix this.
• It requires an input image that has nice contours for any overlapping images to be legible
• I don’t have a case for when I hit record but don’t push one of the byte enables, and I think that causes the board to crash.
• DONE : try rpi power jumper. EDIT : I had to remove the fuse and PFET in order to power everything from the USB C using a 5V 3A rpi supply.

Here is the verilog :

`default_nettype none

module verilog(

      input wire clk,
      input wire  reset,
      output wire LED,
      //buttons
      input wire  rec,
      input wire  [3:0]key,
    
      //rpi pins
      input wire  rpi_clk,
      input wire  rpi_DEN,
      input wire  rpi_h_sync,
      input wire  rpi_v_sync,
      input wire  [1:0]rpi_color,

      //SRAM
      output reg [16:0] addr,
      inout wire [31:0] io,
      // inout wire [3:0] iop,
      output wire SRAM_clk,
      output wire cs_0,
      output wire cs_1,
      output wire ce,
      output wire GW,
      output reg BWE,
      output wire BW1,           
      output wire BW2,         
      output wire BW3,         
      output wire BW4,                          
      output reg ADSP,          
      output wire ADSC,        
      output wire LBO,          
      output wire ADV,          

      //VGA OUT
      output wire  h_sync,
      output wire  v_sync,
      output reg  [3:0] r_out,
      output reg  [3:0] g_out,
      output reg  [3:0] b_out
      );

assign BW1 = key[0];
assign BW2 = key[1];
assign BW3 = key[2];
assign BW4 = key[3];
assign SRAM_clk = clk;
assign GW = 1; // active low ; We want to control individual bytes in this test code
assign cs_0 = 1; //active high; chip always selected.
assign cs_1 = 0; //active low ; chip always selected.
assign ce = 0; //active low ; chip always selected.
assign LBO = 0; // Linear burst sequence selected.
assign ADV = 1; //active low; we don't want addresses to auto advance in this test code.
assign ADSC = 1; //active low; we don't want to auto load address registers, we'll use ADSP instead.
assign h_sync = rpi_h_sync;
assign v_sync = rpi_v_sync;
wire [31:0] data_in;
wire [31:0] data_out;

assign data_in[7:0] = (rpi_color[0] == 1'b1) ? 8'b11111111 : 8'b00000000; // color from rpi
assign data_in[15:8] = (rpi_color[0] == 1'b1) ? 8'b11111111 : 8'b00000000; // color from rpi
assign data_in[23:16] = (rpi_color[0] == 1'b1) ? 8'b11111111 : 8'b00000000; // color from rpi
assign data_in[31:24] = (rpi_color[0] == 1'b1) ? 8'b11111111 : 8'b00000000; // color from rpi

reg [31:0] a, b;

assign io[7:0] = (rec==0) ? a[7:0] : 8'bzzzzzzzz;
assign io[15:8] = (rec==0) ? a[15:8] : 8'bzzzzzzzz;
assign io[23:16] = (rec==0) ? a[23:16] : 8'bzzzzzzzz;
assign io[31:24] = (rec==0) ? a[31:24] : 8'bzzzzzzzz;
assign data_out[31:0] = b[31:0];
   
reg [3:0] counter = 0; //our clock divider

always @(posedge clk) begin

      b[31:0] <= io[31:0];
      a[31:0] <= data_in[31:0];

       if (rec==0) begin // *WRITING* to SRAM (aka recording)

                                            // ADSP should go LOW when SRAM_clk goes HIGH first then HIGH when SRAM_clk goes HIGH on the following cycle...

                                            // ...then, one cycle later, GW should already be LOW to trigger writing

                                            if (counter[0]==1'b0) begin
                                                    ADSP <= 0;         
                                                    BWE <= 0;
                                            end

                                            if (counter[0]==1'b1) begin
                                                    ADSP <= 1;
                                                    BWE <= 0;          
                                            end
     end

     else begin // *READING* from SRAM (aka playback) 
 
                                            // ADSP should go LOW when SRAM_clk goes HIGH...
                                            //...then, once cycle later, GW should already be HIGH to trigger reading
                                            if (counter[0]==1'b0) begin
                                                     ADSP <= 0;
                                                     BWE <= 1;
                                            end

                                            if (counter[0]==1'b1) begin
                                                     ADSP <= 1;
                                                     BWE <= 1;          
                                            end

     end
end

//SRAM address counter
always @(posedge clk) begin

  counter <= counter + 1;

  if (counter[2]) begin

               if(rpi_v_sync) begin // reset the SRAM each time we draw a new frame
                       addr <= 0;
               end
               else begin
                       addr <= addr+1;
               end
  end
end

always @(posedge counter[2]) begin

                              if (rec==1)

                                 begin
                                                                          r_out[0] <= b[7];
                                                                          r_out[1] <= b[7];
                                                                          r_out[2] <= b[31];        
                                                                          g_out[0] <= b[15];
                                                                          g_out[1] <= b[15];
                                                                          g_out[2] <= b[15];
                                                                          b_out[0] <= b[24];
                                                                          b_out[1] <= b[24];
                                                                          b_out[2] <= b[31];
                                 end

                              else if (rec==0)

                                 begin
                                                                          r_out[0] <= a[7];
                                                                          r_out[1] <= a[7];
                                                                          r_out[2] <= a[31];
                                                                          g_out[0] <= a[15];
                                                                          g_out[1] <= a[15];
                                                                          g_out[2] <= a[15];
                                                                          b_out[0] <= a[24];
                                                                          b_out[1] <= a[24];
                                                                          b_out[2] <= a[31];
                                 end
end
endmodule

UPDATES :

• I can do a simple recording that doesn’t jump all over the place.
• I can record and playback 8 bits over time and write that as a byte to the SRAM now.
• I can record images in different banks of memory.
• I can record two bit recordings with two colors.
• I can record and playback in different resolutions
• XOR’ing a recording with the live feed is cool !
• I accidentally managed to get IceCube to infer a BRAM to hold my giant array and it worked
• I can now overlay a ROM image over SRAM recordings
• I can record in BRAM and use all 64K of it !

• I haven’t successfully managed to record 8 images in parallel into the SRAM however.
• I haven’t managed to record an “animation” yet.
• Still no dice with the OV7670 camera.
• I’ve got the HX4K FPGA programmed to blink and LED but am struggling with the screen atm.

*****

I have an opportunity to present this project for the Sketching in Hardware : RESEARCH AND DESTROY! conference in October.

the design and use of physical computing toolkits. tools for creating digital products, environments, and experiences: how to make them, why to make them (and why not), how to use them, how to teach with them, and how to understand their impact.

Serge has the following advice for my project :

It’s about art history, retracing the obsessions different artists had (especially minimalist artists who were trying to reduce the artwork to it’s fundamental parts : paint, canvas, color ) but having the machine rediscover these.

****

Different ways to use a fixed amount of memory (wikipedia) :

Low-fi images using shaded character boxes :

***

BRAM + SRAM recording :

Recording one bit at a time and only writing bytes to the SRAM makes this cool hash patterns :

Recording and then XOR’ing with the live feed :

This glitch that kind of makes cool graphic novel effects from recordings :

Multi-color recordings :

TO DO :

• buy camera for rpi zero
• try more verilog experiments :
  • record and then xor recording with live feed
  • superimpose text over recording or live feed
  • edit a saved image with a cursor
  • fix freezing issue
  • make recording multiple images more efficient (possibly by using DEN and loading recordings into a register like the ROM images?)

META STUFF from friend and artist Annie :

• Don’t have fear about how your project will be received !
• You are following the laws from a bunch of different countries (Industrial Design, Fine Art, Engineering, Hobby tech world). They are presenting too many constraints. Chose to be part of one permissible country, like the Fine Art one, and take the project to its conclusion. In this country you can follow your intuition and desires for the project in the current moment, and avoid getting paralysed speculating about the future. Once you’ve got something you can always chose to go back and redo it super well so that it can become a product.

******

Trying to map out how to make the BRAM line buffer to work with SRAM to do 8 parallel recordings :

I tried to create an SRAM module like the BRAM one but IceCube2 won’t allow a module to have connections with physical pins it appears.

***

OK, I have got rpi recording working reliably 🙂 I also played with different clock divisions, recorded with rpi clock and PB with the FPGA clock, tried recording animations (failed), and tried recording two images in different parts of SRAM.

My process so far : I keep the programmer plugged in but disconnect from the USB after uploading. I reset the FPGA after programming every time (unglug and replug in USB), and delete and recreate + deactivate and reactivate the recording device in OBS studio after unplugging and replugging in the USB each time. I’m using male-female jumpers to go from the rpi to the FPGA. The rpi is powered seperately. I’m using a VGA capture and OBS studio.

Left is the original (Green 5 in DPI mode) and right is the playback (inverted) from SRAM :

Here is the code :

module verilog(

input wire rec,
input wire clk,
input wire rpi_h_sync,
input wire rpi_v_sync,
input wire rpi_color,


output reg [17:0] addr,
inout wire [7:0] io,
output wire cs,
output reg we,
output wire oe,

output wire h_sync,
output wire v_sync,
output reg [3:0] r_out,
output reg [3:0] g_out,
output reg [3:0] b_out
);

assign cs = 0;
assign oe = 0;

assign h_sync = rpi_h_sync;

assign v_sync = rpi_v_sync;

wire [7:0] data_in;
wire [7:0] data_out;

assign data_in[7:0] = (rpi_color == 1'b1) ? 8'b11111111 : 8'b00000000; // color from rpi

reg [7:0] a, b;

assign io = (rec==0) ? a : 8'bzzzzzzzz;

assign data_out = b;


reg [3:0] counter = 0; //our clock divider

//SRAM address counter
always @(posedge clk) begin

counter <= counter + 1;

if (counter[2]) begin

if(rpi_v_sync) begin // reset the SRAM each time we draw a new frame
addr <= 0;
end

else begin
addr <= addr+1;
end
end
end

always @(posedge counter[2]) begin
b <= io;
a <= data_in;
if (rec==0) begin
we <= addr[0]; //not sure why it isn't the inverse of addr[0] but that doesn't make the inverse on 'scope
end
else begin
we <= 1;
end
end

always @(posedge counter[2]) begin


if ((rec==0) && (a==8'b11111111))
begin
r_out[0] <= 1'b0;
r_out[1] <= 1'b0;
r_out[2] <= 1'b0;

b_out[0] <= 1'b0;
b_out[1] <= 1'b0;
b_out[2] <= 1'b0;

g_out[0] <= 1'b0;
g_out[1] <= 1'b0;
g_out[2] <= 1'b0;
end

else if ((rec==0) && (a==8'b00000000))
begin
r_out[0] <= 1'b1;
r_out[1] <= 1'b1;
r_out[2] <= 1'b0;

b_out[0] <= 1'b1;
b_out[1] <= 1'b1;
b_out[2] <= 1'b0;

g_out[0] <= 1'b1;
g_out[1] <= 1'b1;
g_out[2] <= 1'b0;
end

else if ((rec==1) && (b==8'b11111111)) //data_out not b ??
begin
r_out[0] <= 1'b1;
r_out[1] <= 1'b0;
r_out[2] <= 1'b1;

b_out[0] <= 1'b1;
b_out[1] <= 1'b0;
b_out[2] <= 1'b1;

g_out[0] <= 1'b1;
g_out[1] <= 1'b0;
g_out[2] <= 1'b1;
end
else
begin
r_out[0] <= 1'b1;
r_out[1] <= 1'b0;
r_out[2] <= 1'b0;

b_out[0] <= 1'b1;
b_out[1] <= 1'b0;
b_out[2] <= 1'b0;

g_out[0] <= 1'b1;
g_out[1] <= 1'b0;
g_out[2] <= 1'b0;
end
end


endmodule

set_io clk 58

set_io rpi_h_sync 62
set_io rpi_v_sync 61
set_io rpi_color 52

set_io h_sync 76
set_io v_sync 97

set_io rec 47

set_io r_out[0] 91 //for vga
set_io r_out[1] 95 //for vga
set_io r_out[2] 96 //for vga

set_io b_out[0] 87 //for vga
set_io b_out[1] 88 //for vga
set_io b_out[2] 90 //for vga

set_io g_out[0] 75 //for vga
set_io g_out[1] 74 //for vga
set_io g_out[2] 73 //for vga

set_io io[0] 7
set_io io[1] 8
set_io io[2] 9
set_io io[3] 10
set_io io[4] 11
set_io io[5] 12
set_io io[6] 19
set_io io[7] 22

set_io addr[0] 4
set_io addr[1] 3
set_io addr[2] 2
set_io addr[3] 1
set_io addr[4] 144
set_io addr[5] 143
set_io addr[6] 142
set_io addr[7] 141
set_io addr[8] 120
set_io addr[9] 121
set_io addr[10] 24
set_io addr[11] 122
set_io addr[12] 135
set_io addr[13] 119
set_io addr[14] 134
set_io addr[15] 116
set_io addr[16] 129
set_io addr[17] 128


set_io cs 25
set_io oe 23
set_io we 118

And here are some of the documents that were helpful :

***

Successful BRAM implementation :

module ram (din, addr, write_en, clk, dout);// 512x8

parameter addr_width = 15;
parameter data_width = 2;
input [addr_width-1:0] addr;
input [data_width-1:0] din;
input write_en, clk;
output [data_width-1:0] dout;
reg [data_width-1:0] dout; // Register for output.
reg [data_width-1:0] mem [(1<<addr_width)-1:0];

always @(posedge clk)
begin
if (write_en==0)
mem[(addr)] <= din;
else
dout = mem[addr]; // Output register controlled by clock.
end
endmodule

And the top module :

module top (

input wire rec,
input wire FPGA_clk,
input wire rpi_h_sync,
input wire rpi_v_sync,
input wire rpi_color,

output wire h_sync,
output wire v_sync,
output wire [1:0] r_out,
output wire [1:0] g_out,
output wire [1:0] b_out
);

assign h_sync = rpi_h_sync;
assign v_sync = rpi_v_sync;

parameter addr_width = 15;
parameter data_width = 2;

reg [addr_width-1:0] address;
wire [data_width-1:0] data_in;
wire [data_width-1:0] data_out; // Register for output.

assign data_in = {8{rpi_color}};

assign r_out = data_out[1:0];
assign g_out = data_out[1:0];
assign b_out = data_out[1:0];

reg [3:0]counter;

always @(posedge FPGA_clk) begin

counter <= counter + 1;

end

always @(posedge counter[1]) begin

if(rpi_v_sync) begin // reset the SRAM each time we draw a new frame
address <= 0;
end

else begin
address <= address+1;
end
end

ram ram0(
.din(data_in),
.addr(address),
.write_en(rec),
.clk(counter[1]),
.dout(data_out)
);

endmodule

Now to implement the line buffer to store 8 channels of 1 bit recordings !

********

Using the only working Arduino library I could find I can get a kind of VGA out of the OV7670 but it remains extremely slow.

***EDIT I looked into this (https://github.com/AngeloJacobo/FPGA_OV7670_Camera_Interface) and to get a live feed working with an FPGA is a challenge involving multiple clock domains, BRAM, etc. I could work with the images I can capture slowly ?

****

I am preparing to test the TFT screen using these two datasheets :

https://cdn-shop.adafruit.com/product-files/2770/SPEC-CH280QV10-CT_Rev.D.pdf

https://cdn-shop.adafruit.com/datasheets/ILI9341.pdf

I’ve recovered the lost PCB file by using the gerbers sent to PCB way and KiCAD :

***EDIT : I’ve learned something while programming this board. It was floating in some kind of reset state. Always have a blinking light that shows that the board is out of reset. Also, check that IceCube hasn’t randomly rejected and reassigned the pins you have assigned in the pcf.

So far I am only getting grey lines :

I’m using the MCU parallel interface for the moment :

Here is how the colors are sent :

Here is my test file :

//8080 MCU 8-bit bus interface I
// solder all IM sel bits to GND

//D[7:0],WRX,RDX,CSX,DCX

`default_nettype none

module top(
input wire clk,
output reg [7:0] TFT_DB,
output reg [9:0] TFT_DB_GND,
output reg TFT_WRX,
output wire TFT_RDX,
output wire TFT_CSX,
output reg TFT_DCX,
output wire TFT_BACKLIGHT_MOSFET,
output wire TFT_RESX,
output wire LED
);


assign TFT_DB [17:8] = 10'b0000000000; // connect unused DB pins to GND
assign TFT_BACKLIGHT_MOSFET = 1'b1; // turn on
assign TFT_CSX = 1'b0; //chip sel low
assign TFT_RESX = 1'b1; //reset held high (but might need to reset it to get it working according to data sheet?)
assign TFT_RDX = 1'b1; // only writing no reading !

reg [7:0] counter ;
reg [18:0] loop_count ;

always @(posedge clk) begin
counter <= counter + 1;
end

reg [10:0] state;

localparam ADDR = 1'b0;
localparam DATA = 1'b1;

localparam LOW = 1'b0;
localparam HIGH = 1'b1;

localparam MEMORY_WRITE = 8'b00101100; //2Ch
localparam SLEEP_OUT = 8'b00010001; //11h
localparam SOFTWARE_RESET = 8'b00000001; //01h
localparam DISPLAY_ON = 8'b00101001; //29h


// WRITE COMMAND CODE
localparam a1 = 10;
localparam a2 = 12;
localparam a3 = 14;

// WRITE COMMAND CODE
localparam b1 = 20;
localparam b2 = 22;
localparam b3 = 24;

// WRITE COMMAND DATA
localparam c1 = 30;
localparam c2 = 32;
localparam c3 = 34;
localparam c4 = 36;
localparam c5 = 38;
localparam c6 = 40;
localparam c7 = 42;
localparam c8 = 44;


always @(posedge counter[1]) begin

state <= state + 1;

if (state == a1) begin
//t0
TFT_WRX <= HIGH;

end
if (state == a2) begin
//t1
TFT_WRX <= LOW;// transition from high to low
TFT_DCX <= ADDR; // signaling ADDRESS
TFT_DB [7:0] <= SLEEP_OUT; // 11h
end
if (state == a3) begin
//t2
TFT_WRX <= HIGH; // transition from low to high
end


if (state == b1) begin
//t0
TFT_WRX <= HIGH;

end
if (state == b2) begin
//t1
TFT_WRX <= LOW;// transition from high to low
TFT_DCX <= ADDR; // signaling ADDRESS
TFT_DB [7:0] <= DISPLAY_ON; //
end
if (state == b3) begin
//t2
TFT_WRX <= HIGH; // transition from low to high
end


if (state == c1) begin
//t0
TFT_WRX <= HIGH;

end
if (state == c2) begin
//t1
TFT_WRX <= LOW;// transition from high to low
TFT_DCX <= ADDR; // signaling ADDRESS
TFT_DB [7:0] <= MEMORY_WRITE; // 2C << MEMORY WRITE
end
if (state == c3) begin
//t2
TFT_WRX <= HIGH; // transition from low to high
end

// WRITE COMMAND DATA

if (state == c5) begin
//t0
TFT_DB [7:2] <= 6'b101010; //prepare data to write
TFT_WRX <= LOW; // transition from high to low
TFT_DCX <= DATA; // signaling DATA
end
if (state == c6) begin
//t1
TFT_WRX <= HIGH; // transition from low to high
end
if (state == c7) begin
//t2
if(loop_count < 76799) begin
state <= c4; // LOOP times 76 800 (320x240)
loop_count <= loop_count + 1;
end
end
end
endmodule

Over the endless attempts to justify, contextualize, understand this project. Let’s call it art and let it remain mysterious, I’m going to continue doing it whatever happens anyways !

****

Check out the M8 synth :

M8 Tracker Model:02

Their interface is inspired by little Sound DJ for gameboy :

 ****

Some examples of video superposition/collage :

******

Check out these randomly generated 2D Turing Drawing Machines :

http://maximecb.github.io/Turing-Drawings/#

Would be so cool to do this in 3D

*****

I like this artist John Provencher’s project called [test] : https://verse.works/series/test-by-john-provencher

Here is the text explaining the work :

*****

Memory :

This project has centered on electronic memory.

There were periods were the focus was on interface design, open-source project development, on learning about FPGAs, and testing different kinds of synthesizing and filtering circuits, but the project from the beginning has been about sampling in SRAM (after EEPROM, FLASH, and obsolete magnetic media experiments didn’t work).

I’ve tried different sizes of memory (8x 16MB SRAM all the way to the tiniest 512KB SRAM), different divisions of memory banks (from the FPGA addressed SRAM banks to the 8 channel single SRAM discrete logic boad), different means of address incrementing (with discrete counters to FPGA).

I’ve also experimented with different inputs (ADCs to rpi parallel bit interface) and input thresholding (comparators, fast op amps).

The remaining memory experiment is recording an image from a video input and being able to play it back without it jumping around on the screen. After this, recording several images and then doing simple boolean operations on them based on an interactive keyboard.

*****

Conflict minerals used in electronics :

Tungsten :

Tantalum :

Tin :

Gold :

****

Circuit bending (instead of building circuits, modify already built ones) :

• Lick your finger and touch different components while the (non-main voltage plugged-in) machine is turned on and watch/listen for differences.
• Jump two points on the board together while it is outputting something (sound, image). If unknown connections, use & 100ohm or 1k resistor between the points.
• Use a marker on the circuit board itself to mark interesting locations.
• restart the machine if it crashes
• try powering below it’s intended voltage.
• connecting an LED between two points can have an interesting effect.
• RAM chips on samplers can be bent in many different ways with patch bays
• Take photos of the circuit and superpose information on it

Things I’d like to circuit bend :

• DSLR cameras
• webcams
• CCTV cameras
• kid’s toy cameras
• video titler and other old video equipment
• camcorders
• video game consoles
• DVD player

From https://machineproject.com/2014/workshops/digital-cameras-circuit-bending-glitch-art/

The Speak Spellbinder :

*****

A nice looking modular synth case from reddit :

***

Have been recently helping other people on their projects and I noticed some differences between how I work on projects and how some other people do :

• Their goalposts don’t move, and they have a date when they need to have the thing ready.
• They are using technology as a means to do something specific and achieve a desired effect.

This has made me consider going back to my all discrete digital component video sampler, which just needs a built-in screen and the ability to freeze frames for it to be a finished project. Moving away from FPGAs and all the “possibilities” that they create by being reconfigurable, possibilities which somehow end up expanding the project and making it impossible to finish for me. (I’ve always had a tendency to work on the hardware and then get slogged down with the software development side. It’s almost like, because the code is changeable, at some point it doesn’t feel solid and files get lost, I forget what does what, and the project unravels).

I would need to add :

• a screen so it is complete in itself and not needing of external connections to be demo’d.
• a discrete hardware VGA sync generator ? Or should I continue using the rpi sync signals ?
• a way to only record and play back when drawing from the top of the screen to avoid jumping ? This would need to be able to detect when the V sync signals the end of a frame and only allow playback and recording at a specific time (ANDing with CS on the SRAM?).

***

Some little experiments I want to try :

With the Chip Shouter, to mess with the Arduino using VGAX and the FPGA doing VGA and HDMI and see if I can create any interesting visual glitches :

With this Geometric Optics Demo we have at the Cyber Campus, to assign different bit depths of a video signal to different lasers, send the lasers around mirrors and lenses etc, then decode it with laser diodes at the other end. I wonder if I can aim at different logic blocks as they are physically placed in the FPGA ?

Good post on the subject : https://electronics.stackexchange.com/questions/359373/how-to-transmit-data-with-a-laser-beam

Laser sensor module with lens and amp : https://www.amazon.fr/Waveshare-Laser-Receiver-Sensor-Transmitter/dp/B00NJNYQ9G

It could be similar to the Optoglitch project (https://hackaday.com/2019/02/20/optoglitch-is-an-optocoupler-built-for-distortion/), but with lasers for each bit value ? :

For the HDMI bending experiment :

Do imbalances of different degrees create different glitches ? If so, I should map every different possible imbalanced 8 byte combination to a different pixel to explore what pattern it makes !

**********

The tech workshops and classes I’ve done so far :

In terms of being more capable and employable as a teacher, I’d like to go more towards software, especially video games, renderers, shaders, and AI.

To that end, working on a simple procedurally generated cave exploring video game :

https://editor.p5js.org/merlinmarrs/sketches/pfvBYUSGB

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A post shared by jonah marrs (@marrs.io)

I want to make a workshop on 2D game design, based on basic math principles and early video game hardware (so, no libraries, must be smaller than some size, uses tiny memory for sprites and fonts). Check out this under 13KB game design challenge : https://js13kgames.com/

https://www.gamemath.com/book/vectors.html

****

Just checked out the wiki on Video Synthesizers (https://en.wikipedia.org/wiki/Video_synthesizer) and Video Art (https://en.wikipedia.org/wiki/Video_art) and learned some things :

• Doing things in “Real Time” distinguishes video synths from 3D renderers. Video synthesis in analog and even digital was done before computers.
• In Chicago, there were video experiment sessions called “Electronic Visualization Events” 
• “position, brightness, and color were completely interchangeable and could be used to modulate each other during …This led to various interpretations of the multi-modal synesthesia of these aspects of the image in dialogues that extended the McLuhanesque language of film criticism of the time”
• ” Today, address based distortions are more often accomplished by blitter operations moving data in the memory, rather than changes in video hardware addressing patterns. “

****

Cool article on glitches http://beza1e1.tuxen.de/lore/sparkling_tile.html

• The experts solving the problem often are faced with difficult to reproduce glitches. The solution is often to be patient, and observe unexpected correlations systematically. Also deeply understanding the functioning of the systems. Having logs is important to see what happened right before the crash.

*****

Who is my audience ? I am reading lots of posts from hacker news, am I now trying to appear to a more engineering / larger tech literate crowd on the internet ?

How do I make something that people want, how can I build empathy as a designer instead of staying at the selfish research personal project phase ?

I think I am also thinking about how all my interests in tech all boil down to illusions. It is all just man made stuff. I should embrace that it is all a construction and just make pretty things instead of searching for “truth inside the black box”.

***

From this talk ( ), code should be written in the way that that coding language is written in. You shouldn’t try to write python-like code in javascript. Verilog code should look like verilog code.

******

Some mindbending perspective 2D/3D video games :

Viewfinder

Superliminal

Beautiful indie games:

Sword and sorcery

World of Horror, which is made entirely in MS paint :

Papers please :

Thomas was alone (so beautiful how you can play as a pixel, and something so minimal works because of the text overlay and audio):

Pacific Drive (I love the interfaces)

Baba is you (beautiful coding game) :

Minit (love the field of vision with torch effect from Rogue) :

Rainworld :

Keep driving

Some notes :

• The attention to the players experience, and very consciously introducing them to the video game world in a step by step way.
• The importance of sound design in creating atmosphere.
• The fact that it is purely illusion creation, story telling. They let the player live a fantasy.
• There are a finite number of types of games, some include resource foraging, puzzle solving, side scrolling jump based games.
• The importance of lighting, especially glowing lights, shadows, and fog in creating atmosphere.
• 8 bit and 1 bit games are in fashion

  I have been looking at indie games and their construction too. Small scale video games marry tech and art in some a unique way. Game Dev Conf (youtube.com/@Gdconf) is cool to see creators talking about their games.

  On the rainworld game design (youtube.com/watch?v=sVntwsrjNe4). The artist/developer Joar Jakobsson advocates for using programming to create illusions, finding pragmatic, instead of purist, solutions. For their creatures, they have a physics + AI engine first and then a computationally expensive and more complex stylized layer is added on to that. Performance optimization concerns appear to help the creative development of the game. Another insight is that because they are working with made up creatures, no one can fault their representations (we could tell if a horse was moving funny).

  On the Inside rendering (youtube.com/watch?v=RdN06E6Xn9E&t=1885s). Mikkel Gjoel talks about various tricks to create the illusion of fog, quickly render flashlight cones, etc. often in a struggle against 8 bit values that leave bands on the screen. Tricks seem to involve adding different kinds of noise and down/up sampling, using smooth minimum functinos for lighting to eliminate these. The connection between the rendering pipeline, and its bandwidth constraints, and the artistic atmosphere are intertwined. Interesting that this 2.5D game fixes the camera and therefore this allows the artists working on the game to know exactly what will be seen by the player. They also mention how many effects they “stole” from other game developers and are sharing theirs in an open source ethos.

A short Hike GDC talk describes how making the project short and easy to develop, keeping it improvisational, testing + sharing in process work and incorporating feedback, and having a deadline, made it all possible. 

Return of Obra Dinn GDC talk describes how the creator works with an engineering “problem-solving” mentality, and that chosing a technical constraint becomes a fun problem to solve. Describes himself as OCD, and so a basic mechanical core task (often bureaucratic and ostensibly super boring) organizes the game. Inspired by games of old. Has a long term vision of game design, make something so different from other games that this is the only option, and that this won’t change any time soon. Every time he makes a game, picks a completely new style and theme. Don’t be fixated on making everything perfect, even with bugs a thing can become appreciated and a classic. Do something you would enjoy playing.

The GDC for the design of FireWatch talks about making decisions based on how the game should function based on the priorities. If something isn’t directly in line with the main priority, leave it out of the game. They create a boolean database of decisions made by the player as they move through the game that impacts future possibilities of the game space. “Your design must … survive contact with players who have a lifetime of different experiences and assumptions than you”

GDC for the FAITH horror video game has the creator explain that lox fi pixel art is perfect for the horror medium because it is based on the feeling “OMG WTF is that thing?” which is very achievable with a tiny number of pixels. Also, the importance of using black background to create an open space feeling with objects placed within this field.

GDC for 8bit art talks about Color cylcing (https://en.wikipedia.org/wiki/Color_cycling)

GDC for Baba is you talks about the importance of quick game jams in developement.

GDC on solo development (youtu.be/YaUdstkv1RE?si=psfnotyjUE3g4kGF), one speaker talks about the cone of possibilities arising from the pie chart of constraints :

********

Stockhausen

And a great series of video by Hainbach, including some rudimentary vinyl recording devices, bar code card samplers, flanging with two synchronized tape players, and a “Stockhausen speed-run” reproducing beautiful sounds with essentially just a sine oscillator, a splicer and a tape recorder. I realized that this is exactly what I was going for with my early prototypes of the video samplers, trying to construct compositions out of simple parts, and giving one hands-on experience of a time based medium.

*****

Checked out the world of hardware video samplers and discovered that most people use their laptops, so this may be an opportunity !

The OG is the Korg Kaptivator :

Snapbeat https://snapbeat.net/snapbeat-simple-lofi-hardware-sampler/

Here is an open-source one called the r_e_c_r, based on a rpi :

www.20.piksel.no/2020/11/21/r_e_c_u_r-an-open-diy-video-sampler/

And Gieskes arduino video sampler : https://gieskes.nl/visual-equipment/?file=gvs1#p3

I also forgot about Teenage Engineering’s (audio) sampler :

****

Call for Artworks

I’m preparing a submission for the art track of DIS 2025, I am basically proposing slow oscillating VGA monitors. I’m referencing the experimental video art obsession with flowing water and connecting that to the idea of the “oceanic” to line up with the conference theme.

To get most of these effects I used a VCO (like part of a CD4046) and a rudimentary switched capacitor circuit taking in a second out of phase waveform.

Trying to show how visitor’s could interact with the oscillations, and could try to balance them in the middle of the screen :

Showing the circuit for generating the patterns :

****

Watched this teardown of the Formlabs 4 printer, gives an idea of what real product engineering is. There is a big gap between making a quick prototype and making a fully integrated, ready for public use, machine. There is also a big team !

youtube.com/watch?v=cbm03jtWWL0

The conversation turns around the design and manufacturing considerations, the iterations and complexity of the project. It’s a combination of electronics, optics, mechanical engineering, and integration engineering (dissipating heat through the machine, cable management). The design philosophy of making the machine user serviceable is a big constraint. Desgining for things that aren’t supposed to happen, like resin leakage, but may happen. A range of materials (aluminum, stainless steal, magnets, plastics,  and manufacturing processes. There are people who work for months on a single component of the machine, with many iterations. They seemed to try to iterate in house before making expensive tooling. Sensors throughout, for motor rotation, resin level, to detect things being in place. Balancing concerns for robustness, weight, cost, stress resistance, leak protection, fire protection, air flow, heat flow, keeping things level and rigid, making everything work with the existing resin range they have. Using video recordings to observe the operation of parts. Lot of decisions to be made when faced with different design options.

****

FPGA project called Gamebub does everything in python running on an FPGA with a small screen and memory I think :

eli.lipsitz.net/posts/introducing-gamebub/

Also check out this interface for programming FPGAs via USB like they are external drives. Uses CRAM programming :

https://github.com/psychogenic/riffpga

Here is the schematic for noise (Quantum Random Number Generators – Scientific Figure on ResearchGate. Available from: https://www.researchgate.net/figure/Conceptual-representation-of-a-typical-noise-based-random-number-generator-The-voltage_fig6_301899096 [accessed 14 Oct 2024])

Made a random nibbler board based on this circuit :

Here is the board sent to Aisler :

Here assembled :

This is the special hex decoder chip we ordered from ebay :

So far I’ve got something around 200mV of noise. I’ve tried to place that smack in the middle of the 2.5V CMOS level but it remains stable and doesn’t flick back and forth.

I’ve learned that there are challenges with hardware noise, they are sensitive to power supply ripples and to neighbouring sources of electromagnetic radiation.

*****

From pp 558 and starting at 974 AoE

Digital noise with XNORs and big shift registers (64 bits and 8 bits) several bit positions of which that are fed back (called “taps” ) from to the inputs, then low pass filtered and amplified. A register with n bits goes through 2^n -1 states before repeating. It must be shifted higher than the frequency you sample the noise from.

https://en.wikipedia.org/wiki/Linear-feedback_shift_register

The feedback polynomial is determined by the taps chosen (the output is pin 16) :

(1 is because x^0 = 1)

How cool would it be to let people pick the seed, change the taps and the total number of bits operating in the register, and the clocking and sampling frequencies, then to represent the noise on a 2D black and white plane !

Here is the circuit built in Falstad here :

https://tinyurl.com/2ye8zb9f

https://tinyurl.com/2y88tftz

I am then exporting the output into a text file and visualizing it with Processing (after using Notepad++ find and replace to add commas between the values):

...
function setup() {

  createCanvas(200, 1000);

 for (let i = 1; i <= width; i += 1){
   for (let j = 1; j <= height; j += 1){
     if(myarray2[i+j*width] == 5){
       stroke('white');
     }
     else {
        stroke('black');
     }
       point(i, j);
 }
}
}

*********

I should for next time have a schematic of the entire circuit and not just a tinkercad image :

Basically two oscillators get fed into an XOR, the output of which is fed as the SERIAL IN for the 595 through another XOR which also takes feedback in from shift register taps. The second oscillator acts as the clock for the 595.

Here are some slides from the presentation :

**************

Check out this really random :

Really, Really Random Number Generator

******

Other ideas (https://www.mdpi.com/2410-387X/7/2/26) seem to involve multiple ring oscillators :

Here is another article (https://www.mdpi.com/1099-4300/23/9/1168) trying to describe the random using this technique  :

Random Number Generator

********

Vintage hex decoder doesn’t work…

This works though and lets people reconfigure their circuit :

The 8 bit shift register could be replaced with a 16 or more bit register.

******

I’m replacing the non-working hex decoder with a standard BCD to Decimal decoder 74HC42 but then I have the issue of having 4 bits which describe more than 9 chars.

This means that 6/16 of the time there will be no number displayed. I basically need to be able to tell when there is no display so I can keep generating random numbers, while maintaining the same odds for all numbers.

Perhaps I can add logic to detect when D is H while ABC are L (8), and another for when D and A are high and B and C are low (9). I have NOT and XOR gates left over so this should be possible ?

I can do it with an OR and AND using BCD inputs.

******

Also learning KiCAD. Everything very easy so far except for adding external parts.

Preferences > Configurer les Librarie de Symboles, then hit the plus to add a new library (kicad_sym is the file extension).

Then to add the footprint assignment tool : Tools > Assign Footprints using the search bar at the top and double clicking on the part on the right.

To add a 3D package, double click on the origin of the component in board mode and select the 3D tab, then change the orientation :

F3 or View > 3D view :

****

I have a new version of the circuit that gets rid of NOT gates and adds the ability to keep generating numbers until it gets a valid number.

I wonder if I can eliminate the two buttons. Also, how exactly do the DIP switches work here ?

I have had a luxurious summer break and haven’t touched the FPGA video synth for almost two months.

I want to wrap up the project. I’ve just looked through the blog to see what I can take from it :

• I want to expose the FPGA synth in its current state (with minimal or no modifications) at TEI 25′ (didn’t get accepted! Applying to DIS 2025 though) and in Xiao’s space (she doesn’t want electronics there).
• I want to make a kind of research paper / presentation with the HDMI imbalance hack. This is the coolest, most unexpected thing I found and it absolutely requires the FPGA and knowledge of verilog. I don’t want to go further towards the engineering tasks I was engaged in, nor the superficial design activities.

Specificity, and its details, was one of the keys about writing good scripts for the Making of Sopranos documentary Wise Guy. For this reason I don’t think making a framebuffer and then seeing all the different ways I can modify a single input image really makes any sense, there are just too many possibilities and it is too general / too much of an engineering project. Remember this broken screen project with videos playing : https://haoni.art/spin-III.

I could see my series of “design research chapters” as being composed of a series of mini strategies :

• freezing a single computer in time by stretching it up (prepared plotter, prepared 3D prints)
• one input, many different interpretations because machines are idiosyncratic (prepared CRT controller)
• the world view of the computer program (Revit internal IDs)

The natural things to test would be :

• How can I mess with the HDMI color balance, what is the range of possibilities trying different imbalances ?
• How do different screens react ?
• Could this be a kind of hacking of various video protocols like VGA, DVI and HDMI ?

More thoughts on the state of the project :

There is something cheap about putting images on screens, it’s so easy and it’s so ubiquitous that it doesn’t feel special or difficult to do or in any way sacred. At the same time, following the project where it wants to go, I want to work with video because I can with my modest tech skill level.

My video experiments have taught me a few things :

• For abstract animations, bit patterns are cool for digital and simple filters and oscillators are cool for analog. In the spirit of the latter experiments, I made a series of hand-made, wooden-based, simple filters that seemed like a conclusion in themselves. Beyond these it risks getting into very common computer science art territory around math (fractals, etc.) that you can see on shadertoy and processing. From doing p5js workshops (and NO SCHOOL telling me that hardware workshops are always the most enjoyed) I can say that playing with hardware is just more fun than making animations with code.
• Taking iconic cinema as input immediately seems richer, because there is culture and history involved, though I can’t say exactly why I should be distorting a film from the 1960s. Using memory to store video clips in hardware was a breakthrough for me, the severe limitations of SRAM were a useful creative constraint. I haven’t yet been able to take in a video stream and modify it live with the FPGA filters though the VGA camera could be a good solution for that and could lead to new tests.
• On applications : I don’t appear to want to make a cute product : too much polishing, purely technical work, admin and marketing, not enough fun and “design research”. On the other hand, my situation at work allows me to spend money on boards and components so I feel I should take advantage of the opportunity to test ideas in physical form. Hardware video workshops are cool and can work; I’ll test my first technical FPGA workshop in January. I am not sure what to say about this project if I were trying to write a paper. I don’t know if I want to fully engage with the VJ community as I don’t feel part of the music scene. Therefore the project remains hovering between a DIY / hobbyist open-source hardware art project, which doubles as a project to learn technical things, as well as a curated set of images and animations of my “design research” posted on Instagram. In other words, it has to be visually and technically interesting to me.

***************

Reviewing 20th C artists, some notes :

• Some of Duchamp’s readymades were actually called “assisted readymades” if they were altered.
• Décollage like the artwork 122 rue du Temple is an example of ripped collage.
• I feel more aligned with the Bauhaus (Anni Albers, László Moholy-Nagy) than NY based conceptual or minimalist artists.
• Some quotes : Albers “Technique was acquired as it was needed and as a fondation for future attempts. Unburdened by any practical considerations, this play with materials produced amazing results, textiles striking in their novelty, their fullness of color and texture, and possessing often barbabic beauty”. She produced “prototypes for industrial production”.
• MOMA Highlights on Moholy-Nagy : Abstraction is rare and often boring in photography, more interesting is an unfamiliar configuration of form competes for our attention with the subject (between figurative and abstract). Photography is objective, and its unpredictability unveils fresh experiences. Photography challenges old habits of seeing  by showing very distant or very small things, or for looking up or down. Photography has revolutionized modern vision.

• Man Ray Rayographs : “It is impossible to say which plane of the picture are to be interpreted as existing closer or deeper in space. The picture is a visual invention, an image without a real-life model to which we can compare it.” His Rayographs were unpredictable pictorial adventure.
• MOMA Highlights on Stan Brakhage : “In Brakhage’s hands [directly manipulating film stock] became a way to maintain a direct experiential relationship with his chosen medium while refining his art to the essential elements.”
• Add to the video reel : Eisenstein, Man with a movie camera, voyage à la lune, raging bull.

**************

There is another path forward, making an FPGA LVDS LCD controller board. I like that this would be following the logic of the project, going deeper and not running away from the challenge. On the other hand, I’m not convinced it gets much deeper than VGA or HDMI as I’m still dealing with rows and columns, H and V syncs, and colors. It is also potentially a technical hassle like the SD card headache.

You can already see some new colour and texture effects in this DIY project (https://community.element14.com/products/devtools/avnetboardscommunity/b/blog/posts/driving-a-laptop-lcd-using-an-fpga) :

Here are some resources for controlling a Flat panel display (AKA making a FPD-Link converter) with FPGA:

http://web.archive.org/web/20160109020747/http://g3nius.org/lcd-controller/

It looks like these are some examples of the typical signal setups (JEIDAVESA?) :

*****************

Yet another path forward is to complete the tests with the VGA camera input. Check out the pocket glitchomatic which has a camera (solves all the issues with taking video in!!!!)

and this camera called pixless on kickstarter :

This could work nicely with the code I was preparing where each combination of 8 bits selects different logic operations !

Circuit bent digital cameras by glitchedbyproxy :

Then again, couldn’t I just have a webcam on the rpi and output VGA ? No annoying configuration necessary for the camera ! Isn’t the real thing to learn here how to do convolution with the FPGA?

And some cool automata work here by Richard Palethorpe https://richiejp.com/1d-reversible-automata

********

OK, I am trying now to pick back up where I left off pre-summer, notably trying to save rpi video into SRAM through the FPGA in a stable way.

Trying to get the CC version of the board (with SRAM, buttons and RPI dock) back up to speed. I soldered VGA connector and added VGA pins to various .pcf had lying around. None appear to produce anything on the screen. EDIT : This was a pin constraints error. Looked on the scope and the pins weren’t doing anything. It looked at only one of the three input verilog files and ignored the pins from the others. ALWAYS CHECK THE PIN CONSTRAINTS, EVEN IF YOU MAKE A PCF !! This is the issue where IceCube2 can’t seem to deduce the hierarchy of the files and determine which one is TOP. Look at the file name of the bitmap, it should be the top file. Also, be suspicious if it takes too little time to synthesize ! The second issue I had was the vga_sync module not using the incoming clock (instead taking an output from a pll that had since been removed), so nothing was happening.

The rpi is now outputting 640×480 in DPI mode @ 32MHz, I checked on the scope. I think the easiest would be to get the rpi at the same timing. I would like to try again to run custom timings as this appears easier than modifying my fragile FPGA verilog code. (I have forgotten how to get a PLL running). EDIT : I am looking at how the Alhambra sets up a PLL and I’m just editing his pll file with different values : https://github.com/imuguruza/alhambra_II_test/blob/master/vga/vga_test/pll.v. This appears to work stably for turning 12MHz to 25MHz but when I try 100MHz to 32 MHz I run into issues (though perhaps I should just divide the clock in verilog?). I would love to get this rpi DPI calculator working https://nerdhut.de/software/raspberry-pi-dpi-calculator/ or learn to use the new way rpi encodes the screen timings. EDIT : got the rpi DPI calculator installed :

Unfortunately the first try (above) hasn’t yet worked on the rpi (it doesn’t show any pin activity on ‘scope). The best thing working is still the 640×480 at 32MHz with this end of the config :

gpio=0-9=a2
gpio=12-17=a2
gpio=20-25=a2
gpio=26-27=a2

dtoverlay=dpi24
enable_dpi_lcd=1
display_default_lcd=1
dpi_group=2
dpi_mode=87
dpi_output_format=516118
dpi_timings=640 1 44 2 42 480 1 16 2 14 0 0 0 60 0 32000000 1

So how can I divide my FPGA clock from 100MHz to 32MHz ? Tried creating a counter that counted up to 64 MHz and toggled another counter, but I didn’t get any video output (too lazy to debug).

I have a new timing which works (at least on the ‘scope) on the rpi to output 50MHz 800 x 600 :

So here are the two important lines :

dpi_output_format=0x17

dpi_timings=800 0 56 120 64 600 0 37 6 23 0 0 0 72 0 50000000 1

Now I will try to get the FPGA to output these timings…And it works at 800×600 @ 50MHz !

So here are the modifications I made to the vga_sync_test file :

localparam h_pixel_max = 800;

localparam v_pixel_max = 600;

localparam h_pixel_half = 400;

localparam v_pixel_half = 300;

...

// for a 50MHz clock we divide 100MHz by 2

reg [1:0] clk_div = 0;

always @(posedge clk_in)

begin

clk_div <= clk_div + 1;

end
...


vga_sync vga_s(

.clk_in(clk_div[0]), //Dividing by two gives 50MHz

.h_sync(h_sync),

.v_sync(v_sync),

.h_count(h_count),

.v_count(v_count),

.display_en(display_en) // '1' => pixel region

);

endmodule

And the modifications to the vga_sync file :

***********

There are some reasons to remake the CC SRAM board. I guess this shows I am doing incremental design, probably with the hope that this could be a product still one day. Perhaps I should tell myself that I am making a single version change per year ?  :

• The spot where the rpi plugs in blocks the programming pins and the SD card hits the VGA connector.
• A reset button !!!
• 2 pin DPI switch to load different images into FLASH
• Sending rpi_pixel clock to a BUFFERED input on the FPGA (like I am currently doing with the 100MHz clock to pin 49)
• A bigger (and FASTER, like 10ns) SRAM
• Two boards, one with keys, another with circuit. This gives me more space to add things, removes the constraints of the holes passing through the board, gives more buttons, tighter spacing (much more satisfying than the spaced out keys currently), gives it more heft, feels more like a real tool and less like a toy.
• The rpi needs its own power and the power plug can’t currently fit on when it is plugged in. Either I supply the power for the rpi or it is externally powered and I accomodate the plug.
• Currently I am only taking 4 pins from the rpi but ideally I would take 12 color input pins. I also should have h sync, v sync, and DEN wired directly from rpi to FPGA.
• Possibly add a track ball mouse ?
• It would be smart to look into how the rpi camera could be integrated into the design.
• Presumably I will want to move beyond 1280 logic gates to the 4K once I’ve done more tests ?
• Make it so that the Lattice programmer plugs in easily and can’t be plugged in wrong

Another insight : so much time is wasted setting up and resetting up the same setup. Having a permanent version of the screen + cable + rpi + FGPA combination with the wires not moving is going to be essential if I am to actually develop this further. I must switch to seeing this project as a long term one, and I must take my time and do things properly. I should program in reusable modules too !

How cool would it be to have an interface like this on the FPGA :

********

Check out these retro Tectronics screen images :

******

Just trying to make my life easier :

The rpi takes about 2 minutes to enter into video mode in DPI.

I am also being really careful each time I make something worth saving, because IceCube2 edits the files you load, I am making sure to copy and save the files (all verilog files + pcf) I want to keep and to name them so that it is clear what they do. With this structured approach I can build atop my previous work. EDIT : Tommy suggested the obvious : use a git ! Transitioning to this work flow now…Everything is going here :

https://github.com/preparedinstruments/bechamel/tree/main/verilog

I can record from the VGA into SRAM and keep the image mostly frozen. Here is the key line (that basically says only increment the SRAM address if we are in the active pixel area, and also divide it by 2 because the SRAM is only 256K and the total pixels are 480K, and restart the SRAM address counter at the end of the screen) :

always @(posedge clk_div[1]) begin

if (display_en) begin
if( addr < 17'b11111111111111111 && h_count > h_pixel_front_porch_amount && v_count > v_pixel_front_porch_amount && h_count < h_pixel_display && v_count < v_pixel_display && h_count[0]==1 && v_count[0]==1) begin // basically divide the counters because there are 480K pixels but I have 256K SRAM, and only count the active pixel area
addr <= addr+1;
end
else begin
addr <= 0; // I want to restart the counter at the end of each screen draw ?
end
end
end

It produces stable recordings, but they are imperfect :

input

output

So far it’s only working well with vertical lines though…EDIT fixed that !

Instead of incrementing the address, I am now taking the pixel position as the address.

addr <= h_count + (v_count*h_count);

Very noisy but the image is frozen solid with no movement ! But wait, this is wrong because it should be

addr <= h_count + (v_count*800);

EDIT : What seemed like success was in fact failure, I only had stable lines because I was recording only the first line and then resetting the SRAM addr to zero. I fixed that by only making the addr zero once I had reached the v_lines_max. I am getting sketchy recordings but I think it’s because the video is at 50MHz and the memory can’t go that fast?

********

Rereading these Project F FPGA graphics tutorials three things :

• You need to account for memory latency with an offset which you determine through testing when using a framebuffer
• A linebuffer saves you from doing too much memory access
• Shouldn’t calculate the pixel position by multiplying the horizontal_line_count + (vertical_line_count * horizontal_line_width) but should increment the addr value.

*****

I think to get recording w SRAM working I need to first record (and display, and clock the SRAM) with the input pixel clock + h&v syncs, and then switch to playback (and display, and SRAM clocking) with instead the FPGA board clock.

Another option might be to use PLL to synchronize external clocks that are out of phase somehow ? Also, if the clock and the incoming data are not synchronized, it is apparently not optional to double flop the input signal.

Some memory tests I’m preparing :

1. recover the simple design that captured rpi in and played back static images (even if they were distorted)
2. Do this but with BRAM.
3. Use rpi clock to record and display on screen, then switch to fpga clock to pb and display on screen.
4. Try #3 but with a linebuffer not a screen buffer.

Also check out this coding style guideline from nandland which suggests using these prefixes for verilog :

    i_   Input signal 
    o_   Output signal 
    r_   Register signal (has registered logic) 
    w_   Wire signal (has no registered logic) 
    c_   Constant 

Just visited the beautiful greenhouses in Glasgow and saw so many funky patterns and forms in the plants. It made me think about how form is nature, and exploring forms is natural too. I was struck by gradients, fractal patterns, by weirdness, scales of patterns, and the variety of different patterns.

****

Looking through some old video handbooks, here is an image showing the different video protocols on a map :

This shows the behind the screen blanking zones but repositioned to be in the middle of the screen :

**** 

At Christmas Owen gave me some super references and reminded me about the modular synth electronic music world and how they are into analog hardware that produces cool visuals.

The Yoto Player super low res screen and cartridges :

From https://www.peterzimon.com/hog/ :

Here’s my attempt at an interface for a 4×4 version :

Check out this great video about image processing in P5.js :

****

I’ve been trying to develop a simple, tangible AI workshop for designers / artists but so far it looks impossible to do in the way that I want.

The huggingface series is nice, not too technical. The machine vision series has some good background.

********

A great video from Coding Train on Convolutional Neural Nets https://www.youtube.com/watch?v=pRWq_mtuppU

The code is here : https://editor.p5js.org/codingtrain/sketches/GMRfsK7Wn

and also here for Perceptrons : https://www.youtube.com/watch?v=ntKn5TPHHAk

And this is a great article explaining the same concepts : https://ujjwalkarn.me/2016/08/11/intuitive-explanation-convnets/

Basically, take an input image of the correct size, then apply a series of random filters to it. Now use max pooling to further reduce the images and highlight the “features” that they depict. After doing this several times, you end up with a set of features. These are then connected to a perceptron which gets trained to associate different weights to the various features to classify the input image.

Here is another great series of articles explaining ML to artists : https://ml4a.github.io/ml4a/how_neural_networks_are_trained/

********

Kits for art/design + tech workshops / open source projects I could make :

Take project I’ve done / not completed and turn it into a kit ?

https://editor.p5js.org/merlinmarrs/sketches/I9e6HC8_A

I tried and failed somehow at making a single pixel classifier that would just say if an input pixel was closer to dark or closer to light. I wonder if there is an issue taking only a single input for a neuron ?

Finished NO SCHOOL ! Here are some things I learned regarding the board itself :

• the low profile VGA connector is a nightmare, never again.
• the reset button needs to go elsewhere as Lattice IceCube doesn’t like pin 66 for some reason
• the 3D printed cases suck, not necessary and doesn’t have NO SCHOOL on it
• the pads for the bias trim knob kept breaking, not sure if it is bad PCB manufacturing or poor design. Also a bit too hard for beginners to solder this part.
• the portable low power soldering irons sucked for this
• I can remove the caps and 1K resistors for the button debouncing
• the video pass through mode is annoying to set up (needing an audio cable, remembering which pin is H and V sync etc.)
• People like the mechanical keys
• The VCC and GND is useful for powering a breadboard with other video mods

Regarding the hands on video glitching workshop :

• Breadboards and pinout of the VGA connector tough to get the hang of.
• Important to make a safe space – you can’t hurt yourself, nothing valuable here, etc.
• I did a free-style open-ended workshop but still ended up starting with asking the participants to :
  • use jumpers to plug in their board to a VGA cable (though I should have skipped this and went directly to plugging in to the breadboard)
  • use jumpers to plug in their board to a breadboard and then to the VGA cable
  • use switches to turn on or off different channels
  • use pots to attenuate different color channels
  • use coil of wire to make a delay
  • use LM386 to amplify
  • 74*04 to invert
  • Circuit bending the schmitt trigger
  • Mixing signals: 74*86 to XOR, or just pots
• I should have gotten them to put audio in the pass through mode !
• Forgot to ask them to make BLACK AND WHITE from color
• There was no oscilloscope or function generator to work with, I should have brought a logic analyzer too
• Karl Marx was a big hit
• I hand drew some schematics (pinouts of various chips, circuits etc.) and printed them, then would project and draw on the big board the pinouts
• They have difficulty with the translation of schematic to actual connections.
• I can imagine a board made specifically for this workshop which would have an FPGA or Arduino (but without any buttons just as a kind of screen saver) and would connect to a breadboard, breaking out the different pins, where you could do things. This would have gotten around the pain of plugging in jumpers to the VGA connectors, and would be far less work than making the entire FPGA béchamel board. It could be a super basic atmega with just a knob to select patterns.

****

Paul suggests adding to my open source FPGA video synth page :

• A nicer README that explains the project in depth and uses Markdown to make things easier and nicer to read and navigate
• An explanation of how people can use and contribute to the project
• A better organization of the files in the project
• Selecting a licence
• Using git on the PC instead of Github

I really like the idea of doing a super page with gifs explaining what codes do, compiled binaries and commented verilog codes.

I wonder if I could work on a series of separate effects, each with it’s own module, that would allow people to add effects.

Looking in to open source hardware projects for inspiration:

• OPEN MV (https://github.com/openmv/openmv): Uses an 32-bit Arm Cortex-M4 chip with DSPs.
• MUTABLE INSTRUMENTS (https://pichenettes.github.io/mutable-instruments-documentation/) Open source versions of classic eurorack modules

I have rebuilt the git repo and it looks way better now :

What I’ve learned :

• I can import Eagle boards (but not my schematics so far) into KiCAD but I should build using KiCAD from now on for open source projects
• I can take all the energy I was using to make this website and put it into making an awesome README for my project
• A project can almost start with the README, so that it is clear from the beginning what the thing is and what it does

I’ve also promised to send boards to people, perhaps a little prematurely ! Ideally it would be easy for people to upgrade their firmware, this way I could freeze the hardware design and just focus on making code. But this would require giving them a programmer ?

******

Check out this FPGA graphics tutorial : https://projectf.io/posts/fpga-graphics/

Essentially, start by generating a pixel clock for the chosen resolution. Look up standard VGA timings and set up the parameters for blanking etc. Set up a counter and a display enable signal, and then create shapes by using equality operators and colors.

This racing the beam tutorial (https://tomverbeure.github.io/rtl/2018/11/26/Racing-the-Beam-Ray-Tracer.html) explains that if you don’t have enough space for a frame buffer you can have a line buffer, or even a pixel buffer, if you can compute things fast enough. Later in the series using raster font in a simple way, sprites in ROM and scaling them, and creating a simple color LUT.

The screen buffer article is informative : https://projectf.io/posts/framebuffers/ . Especially how to scale up 160×120 framebuffer up to 640×480. Also this one on the three different strategies for making FPGA animations : https://projectf.io/posts/animated-shapes/

This looks like a good FPGA tutorial resource I wasn’t aware of:

• http://asic-world.com/verilog/index.html
• https://projectf.io/tutorials/
• http://fpgacpu.ca/fpga/index.html
• https://zipcpu.com/tutorial/
• http://www.doe.carleton.ca/~gallan/478/pdfs/PeterVrlR.pdf
• https://fpgaer.tech/?p=191

To decode HDMI found this : https://warmcat.com/hardware%20design/hdmi/fpga/2015/10/22/hdmi-capture-and-analysis-fpga-project-3.html

**********

I think this project has been a victim of a certain amount of magical thinking. The machine will only do what it can do and what it is asked to do. Yes, it’s possible to glitch the machine but ultimately there are no surprises unless you don’t fully understand what you’re asking the machine to do. It’s all deterministic. Learning the history of graphics is super cool but you are just reproducing old techniques, there isn’t going to be some hidden type of graphic expression that was missed by everyone that you are going to unlock somehow. It’s just colors on a screen in the end…

It’s ultimately an activity I enjoy, and it is best to share things you enjoy with other people. I should connect with other people making things !

*****

Here’s the final pcf :

// CLOCK

set_io clk_in 49

// HDMI OUT

set_io hdmi_p[0] 139 -io_std SB_LVCMOS
set_io hdmi_p[2] 78 -io_std SB_LVCMOS
set_io hdmi_p[1] 80 -io_std SB_LVCMOS
set_io hdmi_p[3] 137 -io_std SB_LVCMOS

set_io hdmi_n[0] 138 -io_std SB_LVCMOS
set_io hdmi_n[2] 79 -io_std SB_LVCMOS
set_io hdmi_n[1] 81 -io_std SB_LVCMOS
set_io hdmi_n[3] 136 -io_std SB_LVCMOS

// VGA OUT

set_io v_sync 97
set_io h_sync 76

set_io r_out[0] 91
set_io r_out[1] 95
set_io r_out[2] 96

set_io g_out[0] 75
set_io g_out[1] 74
set_io g_out[2] 73

set_io b_out[0] 87
set_io b_out[1] 88
set_io b_out[2] 90

// SOUND OR VGA ANALOG IN

set_io analog_in 56

// POTENTIOMETER IN

set_io pot_in 52

// KEYS IN

set_io key[0] 37
set_io key[1] 38
set_io key[2] 39
set_io key[3] 41
set_io key[4] 42
set_io key[5] 43
set_io key[6] 44
set_io key[7] 45
set_io key[8] 47

// LEDS OUT

set_io green_led 23
set_io red_led 24

// VGA IN

set_io rpi_hsync 34
set_io rpi_vsync 31

module vga_sync_test(
input wire clk_in,
input wire [8:0] key,
input wire rpi_vsync,
input wire rpi_hsync,
input wire analog_in,
inout pot_in,
output [3:0] hdmi_p,
output [3:0] hdmi_n,
output reg [3:0] r_out,
output reg [3:0] b_out,
output reg [3:0] g_out,
output wire h_sync,
output wire v_sync,
output wire red_led,
output wire green_led
);

wire display_en;
//reg [9:0] h_count;
wire [11:0] h_count;
//reg [9:0] v_count;
wire [11:0] v_count;

localparam h_pixel_max = 1280;
localparam v_pixel_max = 960;
localparam h_pixel_half = 640;
localparam v_pixel_half = 480;


reg [4:0] addr;
reg [7:0] data;
reg [7:0] data_out;
always@(addr) begin
case (addr)

0 : data = 0;
1 : data = 16;
2 : data = 31;
3 : data = 45;
4 : data = 58;
5 : data = 67;
6 : data = 74;
7 : data = 77;
8 : data = 77;
9 : data = 74;
10 : data = 67;
11 : data = 58;
12 : data = 45;
13 : data = 31;
14 : data = 16;
15 : data = 0;
16 : data = -16;
17 : data = -31;
18 : data = -45;
19 : data = -58;
20 : data = -67;
21 : data = -74;
22 : data = -77;
23 : data = -77;
24 : data = -74;
25 : data = -67;
26 : data = -58;
27 : data = -45;
28 : data = -31;
29 : data = -16;
default : data = 0;
endcase
end

reg[22:0] div_cntr1;
reg[22:0] div_cntr2;
reg half_sec_pulse;

always@(posedge clk_in)
begin
div_cntr1 <= div_cntr1 + 1;
if (div_cntr1 == 0)
if (div_cntr2 == 0)
begin
div_cntr2 <= 0;
half_sec_pulse <= 1;
end
else
div_cntr2 <= div_cntr2 + 1;
else
half_sec_pulse <= 0;

end


always @(posedge half_sec_pulse) begin

data_out <= data;
addr <= addr + 1;
if(addr == 29)
addr <= 0;

end

// FOR AUDIO IN INTERACTION
assign red_led = analog_in;
assign green_led = analog_in;

// FOR KEY INTERACTION key[8:0]

// FOR POT INTERACTION

reg [15:0] adc_count= 0; //16 bits to count how long it's taking to charge. 32,768 is the max value. 1 extra MSB bit for just discharging the cap.
reg [14:0] pot_value= 0; //to store cap charge time value
reg [14:0] final_pot_value= 0;

wire adc_in;
reg adc_sample = 1; //first time through we want to sample the cap value

wire adc;


assign pot_in = (adc_sample) ? 1'bZ : 1'b0;
assign adc_in = pot_in;

// for a 25MHz clock we divide 100MHz by 4
reg [1:0] clk_div = 0;

always @(posedge clk_in)
begin
clk_div <= clk_div + 1;
end


always @(posedge clk_div[1]) begin //25MHz clock

adc_count <= adc_count + 1; // start counting

if(adc_count>=16'b1000000000000000 )begin // once we have rolled over 15 bit counter...

adc_sample <= 1'b0; // ...discharge cap for a while to restart the process.

end

else begin

adc_sample<=1'b1; //put cap pin in high 'Z'

if(adc_in==1'b1) begin // if cap charged...

pot_value[14:0]<=adc_count[14:0]; //store this value in pot


end

end

end


// FOR SOUND INTERACTION

// FOR AUDIO IN INTERACTION

//Check if we can create RGB colors
always @(posedge clk_in) begin



if (display_en) begin
if (h_count < h_pixel_half + data_out
&& v_count < v_pixel_half - data_out) begin
//Assign here your test color



//pot changing colors
case(pot_value[14:13])

2'b00: begin //yellow
r_out <= 3'b010;
g_out <= 3'b110;
b_out <= 3'b011;
end
2'b01: begin //cyan
r_out <= 3'b011;
g_out <= 3'b100;
b_out <= 3'b001;
end
2'b10: begin //magenta
r_out <= 3'b110;
g_out <= 3'b110;
b_out <= 3'b011;
end
2'b11: begin //blue
r_out <= 3'b010;
g_out <= 3'b111;
b_out <= 3'b111;
end

default: begin // white
r_out <= 3'b010;
g_out <= 3'b010;
b_out <= 3'b011;
end
endcase




end else if (h_count > h_pixel_half - data_out
&& v_count < v_pixel_half + data_out) begin

if (analog_in == 1) begin
//Assign here your test color
r_out <= 3'b010;
g_out <= 3'b110;
b_out <= 3'b011;
end
else begin
r_out <= 3'b001;
g_out <= 3'b010;
b_out <= 3'b100;
end
end else if (h_count < h_pixel_half - data_out
&& v_count > v_pixel_half - data_out) begin
//Assign here your test color
r_out <= key[2:0];
g_out <= key[5:3];
b_out <= key[8:6];
end else begin
//Assign here your test color
r_out <= 3'b010;
g_out <= 3'b010;
b_out <= 3'b010;
end
end else begin
r_out <= 3'b000;
g_out <= 3'b000;
b_out <= 3'b000;
end
end

vga_sync vga_s(
.clk_in(clk_in), //12MHz clock input
.h_sync(h_sync),
.v_sync(v_sync),
.h_count(h_count),
.v_count(v_count),
.display_en(display_en) // '1' => pixel region
);

endmodule

module ram (din, write_en, waddr, wclk, raddr, rclk, dout);// 32768‬ x 2

parameter addr_width = 15; // to access all 32768‬ bits of the address
parameter data_width = 2;
input [addr_width-1:0] waddr, raddr;
input [data_width-1:0] din;
input write_en, wclk, rclk;
output reg [data_width-1:0] dout;
reg [data_width-1:0] mem [(1<<addr_width)-1:0]
;

always @(posedge wclk) // Write memory.
begin
if (write_en)
begin
mem[waddr] <= din; // Using write address bus.
end
end
always @(posedge rclk) // Read memory.
begin
dout <= mem[raddr]; // Using read address bus.
end
endmodule

addr <= (((hc-hbp)>>2)+(((vc-vbp)>>2)*160));

assign data_in[7:0] = (again_xnor[7:0] > key[7:0]) ? 8'b11111111 : 8'b00000000;

this :

if ((rec==0) && (a>=8'b10000000))

to this :
if ((rec==0) && (a==8'b00000000))

localparam h_pixel_total = 800;
localparam h_pixel_display = 640;
localparam h_pixel_front_porch_amount = 16;
localparam h_pixel_sync_amount = 96;
localparam h_pixel_back_porch_amount = 48;

localparam v_pixel_total = 525;
localparam v_pixel_display = 480;
localparam v_pixel_front_porch_amount = 10;
localparam v_pixel_sync_amount = 2;
localparam v_pixel_back_porch_amount = 33;

localparam h_pixel_max = 640;
localparam v_pixel_max = 480;
localparam h_pixel_half = 320;
localparam v_pixel_half = 240;

...


// for a 25MHz clock we divide the 100MHz clk_in by 4
reg [1:0] clk_div = 0;

always @(posedge clk_in)
begin
clk_div <= clk_div + 1;
end
...

vga_sync vga_s(
.clk_in(clk_div[1]), // giving vga_sync the 25MHz clock 
.h_sync(h_sync),
.v_sync(v_sync),
.h_count(h_count),
.v_count(v_count),
.display_en(display_en) // '1' => pixel region
);

endmodule

addr <= (((hc-hbp)>>1)+(((vc-vbp)>>1)*320));

...
else
begin
hc <= 0;
if (vc < vlines) begin
vc <= vc + 1;
screen_count <= screen_count + 1;
end
else
vc <= 0;
end
end
else begin
c0_high_speed <= {2'b00, c0_high_speed[9:2]};
c1_high_speed <= {2'b00, c1_high_speed[9:2]};
c2_high_speed <= {2'b00, c2_high_speed[9:2]};
clk_high_speed <= {2'b00, clk_high_speed[9:2]};
latch_high_speed <= latch_high_speed + 1'b1;
end
end

always @(posedge latch_high_speed[2]) // display 100% saturation colourbars
begin

case(screen_count[9])

1'b0 : multiplier = 1;
1'b1 : multiplier = 2;

default : multiplier = 1;

endcase

// first check if we're within vertical active video range
if (vc >= vbp && vc < vfp)
begin
// now display different colours every 80 pixels
// while we're within the active horizontal range
// -----------------
if(hc >= hbp && hc < hfp) begin

//pixel <= heart[(((hc-hbp)>>2)+(((vc-vbp)>>2)*160))];
addr <= (((hc-hbp)>>1)+(((vc-vbp)>>1)*320*multiplier));

...

...

case(key[7:6])
2'b00: multiplier = 1;
2'b01: multiplier = 2;
2'b10: multiplier = 3;
2'b11: multiplier = 1;

default: multiplier = 1;
endcase

if (vc >= vbp && vc < vfp)
begin

if(hc >= hbp && hc < hfp) begin

addr <= (((hc-hbp)>>1)+(((vc-vbp)>>1)*320*multiplier));

...

...

case(key[7])
2'b0: offset = 0;
2'b1: offset = 78000;
default: offset = 0;
endcase


if (vc >= vbp && vc < vfp)
begin

if(hc >= hbp && hc < hfp) begin

addr <= (((hc-hbp)>>1)+(((vc-vbp)>>1)*320)+ offset);

...

if (vc < vlines) begin
vc <= vc + 1;
frame <= frame + 1;
if(screen_count>12)begin
screen_count <= 0;
end
if (frame > 6000) begin
screen_count <= screen_count + 1;
frame <= 0;
end
end

...

addr <= (((hc-hbp)>>2)+(((vc-vbp)>>2)*160)+(offset*screen_count));

 PIX_SRC s (replacement) PIX_NOT(PIX_SRC) ~s (replacement with bit inversion) PIX_SRC | PIX_DST s | d PIX_SRC & PIX_DST s & d PIX_SRC ^ PIX_DST s ^ d PIX_NOT(PIX_SRC) | PIX_DST ~s | d PIX_NOT(PIX_SRC) & PIX_DST ~s & d PIX_NOT(PIX_SRC) ^ PIX_DST ~s ^ d PIX_SRC | PIX_NOT(PIX_DST) s | ~d PIX_SRC & PIX_NOT(PIX_DST) s & ~d PIX_SRC ^ PIX_NOT(PIX_DST) s ^ ~d PIX_NOT(PIX_SRC | PIX_DST) ~(s | d) PIX_NOT(PIX_SRC & PIX_DST) ~(s & d) PIX_NOT(PIX_SRC ^ PIX_DST) ~(s ^ d

After failing to do various “simple” things in verilog, I’m doing a little refresher course. Resources :

• https://hackaday.com/series_of_posts/williams-icestick-tutorial/
• https://www.doulos.com/knowhow/verilog_designers_guide/
• https://vol.verilog.com/

//VERILOG CODING PRACTICES

//verilog is case sensitive !

reg THIS; // not the same as this !
reg this;

//to repeat : {repeat_count{}}

vec[1:20] = {4{5'b10110}};

**********

// this is better than just [23:0] for readability :
parameter buswidth = 24;
input [buswidth-1:0] bus;

//this is better than just 47:0 for readability :
reg [8*6:1] string6;

***********

//scalars (single bit vs vectors which are multi-bit) can have the following values:

0 - logic zero (false)
1 - logic one (true)
x - unknown value
z - high-impedance value

// therefore an equality test can return unknown if one of the operands is x or z !

if (expression) is evaluated :

0 false
1 true
x false
z false

//nets receive signal values
//net or register port expressions send values

//regs need initial conditions, wires need NOT to have initial conditions assigned.

//keep in mind if you're making combinational or sequential logic !

*******

//legal assignments :

lhs = rhs;
lhs[bit] = rhs;
lhs[partmsb:partlsb] = rhs;
{lhs1, lhs2} = rhs;
***********
//for a null operation use the semi-colon :

if (control)
;
else
x = f(y);

*******
//You can give names to binary combinations :

`define A 3'b001
`define B 3'b010
`define C 3'b100

initial state = `A;

********
//You can deassign :

else if (!preset)
assign q = 1;
else
deassign q;

*********

// in simulation you can use the $random system function

integer rand;
rand = $random;

*************
//don't do this :
assign n1 = w1 + f(w2) + g(w3);

//do this instead :
assign t2 = f(w2);
assign t3 = g(w3);
assign n1 = w1 + t2 + t3;

************
//this :
wire AB;
assign AB = A & B;

// can be written like this :
wire AB = A & B;

**************

//This creates an implicit sensitivity list that contains all the signals whose values are 
//read in the statements of the always block :

always @(*)

//Remember : To synthesize combinational logic using an always block, 
//ALL inputs to the design must appear in the sensitivity list.

********

// LATCHES 
// https://nandland.com/how-to-avoid-creating-a-latch/
//Latches are bad, they are combinational and not driven by a clock. If you use a clocked process 
//you avoid the possibility of unintentionally making a latch.

//All combinational processes need to explicit assignments for every possibility. Don't leave a conditional test
//that has only an if and no else to account for the other possible values.

// TEST BENCHES

//for test benches use # to make things happen at certain times :

x = 0;
#10 x = x + 1;
#20 x = x + 2;
#30 x = x + 3;
#20 x = x + 2;
#10 x = x + 1;

time:       value of x :
0                0
10               1
30               3
60               6
80               8
90               9

// for test bench clocks :
always
begin
#period/2 clk = ~clk;
end

// CLOCK BUFFERING 

Do external clocks need buffering ? If so, is this how to buffer an external clock ?

SB_GB_IO gb_io1 (
.PACKAGE_PIN( clk ),
.GLOBAL_BUFFER_OUTPUT( gclk )
);

...or with extra params ?

SB_GB_IO gb_io1
( .PACKAGE_PIN(clk),
.OUTPUT_ENABLE(1'b1),
.GLOBAL_BUFFER_OUTPUT(gclk)
);
defparam gb_io1.PIN_TYPE = 6'b000001;
defparam gb_io1.PULLUP = 1'b0;
defparam gb_io1.NEG_TRIGGER = 1'b0;
defparam gb_io1.IO_STANDARD = "SB_LVCMOS";

// MEMORY

// to instantiate 1 bit memory :
reg membits [1023:0]; // 1024 1-bit registers

//You can't take a bit-select or part-select of a memory element.
//Thus, if you want to get the 3rd bit out of the 10th element of a memory, 
//you need to do it in two steps:

reg [0:31] temp, mem[1:1024];
...
temp = mem[10];
bit = temp[3];

// RACE CONDITIONS 
// This code produces a 'race condition' :

always @(posedge clock) always @(posedge clock)
dff1 = f(x); dff2 = dff1;

// it can be fixed with non-blocking assignments :

always @(posedge clock) always @(posedge clock)
dff1 <= f(x); dff2 <= dff1;

//CROSSING CLOCK DOMAINS 

one solution is to double latch everything.

**********

I am systematically trying to figure out why I can’t take rpi input and redisplay it with the simple HDMI code.

I am starting by sending signals in a pass through way like this :

always @(posedge rpi_pixel_clock) begin

b_in_repeat <= b_in;

end

I get the same input signal but one clock later on the ‘scope so as expected.

 Thoughts on this as a product now that SD card seems possible :

• I could put “sprites” like the bechamel logo and some numbers in some location in memory.
• I could be able to save screen shots on the SD card with a button combo.
• Could there be a kind of database, which would be like how rhino saves files of 3D models one is working on ?
• Am I making a mini computer (ALU, slow big memory, fast SRAM, user interface, screen output) ? What do I think about a scroll wheel and a mini screen then ?
• What could I do with a stack of images from the SD card ?

Just a reminder of what a fully fleshed out video system looks like with the Gameduino : https://excamera.com/files/gameduino/synth/doc/gen/poster.pdf

*********

Checking-in with my project goals for 2024.

• This year the goal was to have a finished open-source project that could be shared with people online or as a kit/product via prepared instruments.com. I would be able to show it to students as an example of a finished design/engineering project that I have completed. The idea would be to stabilize the design, to stop making endless boards, and begin exploring more verilog codes that run on it.

Currently, the Cyber Campus version of the board is basically complete enough to transition into just trying new code. There is just the SD card that remains before the object has a feel of being an independent finished object that isn’t dependent on any other products (like rpi) to function.

Perhaps a distinction between the product, art and workshop kit would be useful :

Kit : reprogrammable, built around the rpi, solderable by beginners, etc.

Product : HDMI IN (a compromise would be that chip that handles everything like the TFP401PZP) and HDMI OUT, plug and play with modern tech. Has a larger FPGA to be able to do more cool stuff.

Art : The Cyber Campus version has everything I need to have fun with new codes, especially ones that interact with time and sequence (like temporal compression?), like differences between images in time impacting the kinds of transformations instead of staying with just static filters.

*********

I need to make the SD card code more generalizable with a function that takes CMD IN.

Here is the command format :

For example CMD8, the first byte is 01001000 with : 0 (start bit) + 1 (tx bit) + 010000 (six bits of the CMD number 8 in binary). After this are 32 bits of arguments (such as address you want to select) the 6 bit CRC7 and then 1.

NOTE ** I may need to change the speed from 50KHz to 100KHz or 200KHz for things to work. I am unclear about when I need to send ticks but forum user writes this :

; There must be 8 clocks after
; * a command with no response
; * the response of a command with a response
; * the end of a read data block
; * the CRC status token on a write

Here is the sequence of commands I have so far :

//TICKS
parameter TICKS = 48'b11111111_11111111_11111111_11111111_11111111_11111111;

//CMD0 “GO_IDLE_STATE”
parameter CMD0 = 48'b01000000_00000000_00000000_00000000_00000000_10010101;

//CMD8 “SEND_IF_COND”
parameter CMD8 = 48'b01001000_00000000_00000000_00000001_10101010_10000111;

//CMD55 “APP_CMD”
parameter CMD55 = 48'b01110111_00000000_00000000_00000000_00000000_01100101;

//ACMD41 “SD_SEND_OP_COND”
parameter ACMD41 = 48'b01101001_01000000_00010000_00000000_00000000_11001101;

//CMD2 “ALL_SEND_CID”
parameter CMD2 = 48'b01000010_00000000_00000000_00000000_00000000_01001101;

//CMD3 “SEND_RELATIVE_ADDR”
parameter CMD3 = 48'b01000011_00000000_00000000_00000000_00000000_00100001;

//CMD7 “SELECT/DESELECT_CARD”
parameter CMD7 = 48'b01000111_00000000_00000000_00000000_00000000_CRC+1; // need to generate my own CRC for this

//CMD17 “READ_SINGLE_BLOCK”
parameter CMD17 = 48'b01010001_00000000_00000000_00000000_00000000_CRC+1; 

NOTE ** There is a read multiple block command CMD18 READ_MULTIPLE_BLOCK that takes a 32 bit address and continuously transfers data blocks until interrupted by the STOP_TRANSMISSION command. By default sends 512 bytes followed by a CRC.

I am currently breaking up the code into cycles of 48 clock pulses to send and receive commands in sequence.

counter <= (counter==47) ? 0 : counter+1; // to count the steps in the sending of a single CMD
phase <= (counter==47) ? phase+1: phase; // to count how many CMDs we have sent

Each command is currently sent in order by checking the phase. For example :

if (phase == 8) begin
      rec <= 1; // set CMD to output
      CMD <= ACMD41[counter]; // iterate through the 48 bit command
end

Listening to input is tougher because of my poor understanding of inout, I am using inout to define the CMD pin. If we are receiving it is put in a high Z state.

assign CMD = rec ? CMD : 1'bz;

I am not sure if this will work :

if (phase == 9) begin
      rec <= 0; // set CMD inout pin to high Z
      data_in[counter] <= CMD; //store the data in data_in
end

Here I’m trying to check if a ready bit 31 is still unset :

if ((data_in & (1<<31))==0)

Here I’m trying to compose the CMD7 by concatenating the appropriate bytes.

//CMD7 “SELECT/DESELECT_CARD”
if (phase == 16) begin
   rec <= 1;
   RCA[15:0] = data_in[31:15]; // retrieve the RCA from the previous response
   CMD7[47:0] = {8'b01000111,RCA[15:0],16'b0000000000000000,CRC+1}; // compose CMD7 from parts
   CMD <= CMD7[counter]; // send the command
end

****

I’m on this site to calculate the CRC7 (https://www.ghsi.de/pages/subpages/Online%20CRC%20Calculation/)

• First I enter the CRC polynomial which for the SD card is x7 +x3 + 1
• Then I translate the 5 bytes I want to send into hex
• The 7 bit value generated at the end of the page is then added to the end of the message plus the end bit (1)

I need to figure out how to incorporate the CRC in verilog for certain commands however :

The above website automatically generates this verilog code that takes one bit at a time :

// ==========================================================================
// CRC Generation Unit - Linear Feedback Shift Register implementation
// (c) Kay Gorontzi, GHSi.de, distributed under the terms of LGPL
// ==========================================================================
module CRC_Unit(BITVAL, BITSTRB, CLEAR, CRC);
input BITVAL; // Next input bit
input BITSTRB; // Current bit valid (Clock)
input CLEAR; // Init CRC value
output [6:0] CRC; // Current output CRC value

reg [6:0] CRC; // We need output registers
wire inv;

assign inv = BITVAL ^ CRC[6]; // XOR required?

always @(posedge BITSTRB or posedge CLEAR) begin
if (CLEAR) begin
CRC = 0; // Init before calculation
end
else begin
CRC[6] = CRC[5];
CRC[5] = CRC[4];
CRC[4] = CRC[3];
CRC[3] = CRC[2] ^ inv;
CRC[2] = CRC[1];
CRC[1] = CRC[0];
CRC[0] = inv;
end
end

endmodule

I am not sure exactly how to feed this module one bit at a time. I also feel unsure about how to properly incorporate modules from different files.

****

Here is my test code (once the timescale is uncommented) that I’m hoping will not require CRC (I’ll just look on the oscilloscope to see what the RCA is and then use that). It is the simplest possible setup.

Possible things that need changing :

• I am not waiting to see if bit 31 is set after sending ACMD41, so I probably will need to add a delay here ? *EDIT* I am getting a busy bit 31 the first time I ask at the moment.
• 8 clock ticks instead of 48 ? *EDIT* DONE
• No clock ticks after certain commands?
• The RCA (and CRC) if it is not 0001
• The block address (and CRC) if it is not 0

//-----------------------------------------------------------------
// - Attempt at SD 1 bit communication -
//CMD0 “GO_IDLE_STATE”
//CMD8 “SEND_IF_COND”
//CMD55 “APP_CMD”, ACMD41 “SD_SEND_OP_COND” with argument 40100000 (HCS=1, voltage = 3.3).
//The R3 response has HCS and the supported voltages set. Repeat until bit 31 of the response is 1.
//CMD2 “ALL_SEND_CID” with argument 00000000. The R2 response has the CID. I ignore it.
//CMD3 “SEND_RELATIVE_ADDR” with argument 00000000. The R6 response contains the RCA and some status that I ignore.

//The card is now in the stand-by state. Reading a block is accomplished by
//CMD7 “SELECT/DESELECT_CARD” with argument bits 31-16 = the RCA you were given, 15-0 = 0. The R1b response I ignore.
//CMD17 “READ_SINGLE_BLOCK” with argument = the block address.
//The R1 response I ignore, but there will also be the block data.
//Keep toggling the clock, and you’ll eventually see a start bit followed by a block of data and a CRC.
//-----------------------------------------------------------------

`default_nettype none // disable implicit definitions by Verilog
//`timescale 1us/1ns

module top(
input wire clk100,
input wire reset,
//input reg DAT,
output reg SCK,
output reg CMD
);

//CMD0 “GO_IDLE_STATE”
parameter CMD0 = 48'b01000000_00000000_00000000_00000000_00000000_10010101;

//CMD8 “SEND_IF_COND”
parameter CMD8 = 48'b01001000_00000000_00000000_00000001_10101010_10000111;

//CMD55 “APP_CMD”
parameter CMD55 = 48'b01110111_00000000_00000000_00000000_00000000_01100101;

//ACMD41 “SD_SEND_OP_COND”
parameter ACMD41 = 48'b01101001_01000000_00010000_00000000_00000000_11001101;

//CMD2 “ALL_SEND_CID”
parameter CMD2 = 48'b01000010_00000000_00000000_00000000_00000000_01001101;

//CMD3 “SEND_RELATIVE_ADDR”
parameter CMD3 = 48'b01000011_00000000_00000000_00000000_00000000_00100001;

//CMD7 “SELECT/DESELECT_CARD”
parameter CMD7 = 48'b01000111_00000000_00000001_00000000_00000000_11011101; // ASSUMING RCA IS 0001

//CMD17 “READ_SINGLE_BLOCK”
parameter CMD17 = 48'b01010001_00000000_00000000_00000000_00000000_01010101; // ASSUMING ADDR ZERO EXISTS

//CMD18 “READ_MULTIPLE_BLOCK”
parameter CMD18 = 48'b01010010_00000000_00000000_00000000_00000000_11100001; // ASSUMING ADDR ZERO EXISTS


//some counters
reg [9:0] counter=0;
reg [9:0] phase=0;
reg [7:0] q=0;


// divide 100MHz clock by 255 to equal 196.0784315 KHz which is in the 100KHz - 400KHz range

always @(posedge clk100) begin

q <= q+1;
if(q == 0) begin
SCK <= ~SCK;
end
end

//to count 48 SCK cycles and also how many which step of the communication sequence we're on


always @(posedge SCK) begin


//send 8 ticks
if (phase == 0) begin

counter <= counter+1;

if (counter <= 7) begin
CMD <= 1'b1;
end
else begin
counter<=0;
phase<=phase+1;

end
end

//send CMD0

if (phase == 1) begin

counter <= counter+1;

if (counter <= 47) begin
CMD <= CMD0[47-counter];
end
else begin
counter<=0;
phase<=phase+1;

end

end


//send 8 clock ticks while CMD high

if (phase == 2) begin

counter <= counter+1;

if (counter <= 7) begin
CMD <= 1'b1;
end
else begin
counter<=0;
phase<=phase+1;

end

end

//send CMD8


if (phase == 3) begin

counter <= counter+1;

if (counter <= 47) begin
CMD <= CMD8[47-counter];
end
else begin
counter<=0;
phase<=phase+1;
end


end


//set CMD to input

if (phase == 4) begin


counter <= counter+1;

if (counter <= 47) begin
CMD <= 1'bz;
end
else begin
counter<=0;
phase<=phase+1;

end


end



//NEED THIS ? send 8 clock ticks while CMD high

if (phase == 5) begin

counter <= counter+1;

if (counter <= 7) begin
CMD <= 1'b1;
end
else begin
counter<=0;
phase<=phase+1;

end

end

//send CMD55


if (phase == 6) begin

counter <= counter+1;

if (counter <= 47) begin
CMD <= CMD55[47-counter];
end
else begin
counter<=0;
phase<=phase+1;

end



end

//listen to response

if (phase == 7) begin

counter <= counter+1;

if (counter <= 47) begin
CMD <= 1'bz;
end
else begin
counter<=0;
phase<=phase+1;

end


end


//NEED THIS ? send 8 clock ticks while CMD high

if (phase == 8) begin

counter <= counter+1;

if (counter <= 7) begin
CMD <= 1'b1;
end
else begin
counter<=0;
phase<=phase+1;

end

end

//send ACMD41


if (phase == 9) begin

counter <= counter+1;

if (counter <= 47) begin
CMD <= ACMD41[47-counter];
end
else begin
counter<=0;
phase<=phase+1;

end

end

//listen to response and check bit 31 is 1

if (phase == 10) begin


counter <= counter+1;

if (counter <= 47) begin
CMD <= 1'bz;
end
else begin
counter<=0;
phase<=phase+1;

end

end


//send CMD2

if (phase == 11) begin

counter <= counter+1;

if (counter <= 47) begin
CMD <= CMD2[47-counter];
end
else begin
counter<=0;
phase<=phase+1;

end


end


//listen to 136 bit CID CMD from SD

if (phase == 12) begin

counter <= counter+1;

if (counter <= 135) begin
CMD <= 1'bz;
end
else begin
counter<=0;
phase<=phase+1;

end

end


//send CMD3

if (phase == 13) begin

counter <= counter+1;

if (counter <= 47) begin
CMD <= CMD3[47-counter];
end
else begin
counter<=0;
phase<=phase+1;

end

end

if (phase == 14) begin

counter <= counter+1;

if (counter <= 47) begin
CMD <= 1'bz;
end
else begin
counter<=0;
phase<=phase+1;

end

end

//CMD7 “SELECT/DESELECT_CARD”
if (phase == 15) begin


counter <= counter+1;

if (counter <= 47) begin
CMD <= CMD7[47-counter];
end
else begin
counter<=0;
phase<=phase+1;

end

end

//listen to CMD from SD

if (phase == 16) begin


counter <= counter+1;

if (counter <= 47) begin
CMD <= 1'bz;
end
else begin
counter<=0;
phase<=phase+1;

end

end

//CMD17 “READ_SINGLE_BLOCK” with argument = the block address.

if (phase == 17) begin



counter <= counter+1;

if (counter <= 47) begin
CMD <= CMD17[47-counter];
end
else begin
counter<=0;
phase<=phase+1;

end

end

if (phase == 18) begin



counter <= counter+1;

if (counter <= 47) begin
CMD <= 1'bz;
end
else begin
counter<=0;
phase<=phase+1;

end

end

// Should start to see data coming in on the DAT pin !!
if (phase >= 19) begin

// DAT pin

end


end

endmodule

The sequence for ModelSim was :

For my first finished product for prepared instruments (preparedinstruments.com), the goal is to remake the hardware 7ch palimpsest.OS SRAM but with :

• a square keyboard grid interface like the PEW design (knobs and switches replaced with keys)
• an aluminium PCB substrate (with a single-sided board) ?
• a simpler amp in path with only one pot
• all 0805 and SOIC packages

I’ve been thinking about it and I can’t say that this board will be inexpensive. If you want to explore video synthesis inexpensively, you should do things for free in code on the computer. This is a physical digital logic / analog device so it will cost money.

Because it’s the first in a series, I would like this board to set the format of the others. I’m imagining them all like Ritter Sport square bars. Like the eurorack format, I would like to have a standard way of powering the boards and I need to decide on a way of jumping between the boards (VGA cables?).

I’d also like the boards and the packaging to be ecologically responsible. I don’t know if this means using an aluminium substrate (which can be easily recyclable in theory) or a flexible circuit (with either a thin plastic or stained steel stiffener – in theory recyclable).

Looking back on the synths from this year, I never really wanted to code/configure the things I made. Doing hardware synths makes sense as it puts me in a different spot in the market place, makes the designs harder to just copy, and it allows me to savour the suffering in the design process. The analog function board was ultimately underwhelming. Going the direction of installation pieces isn’t satisfying because they are too site-specific and local for my project I feel (though perhaps making films is the solution here). The gameboy design made me feel bad about the waste of buying a mini screen and the software challenge of communicating with it seems not crucial to my project (but I will finish at least the physical side of the project to test the layout). The memory boards were the coolest, and of them the layering board is the most elegant design and the most interesting in what it can do.

Here’s the new site where the béchamel will appear:

Thoughts from Vincent :

• Connect with other people making video synths !
• Try shooting some of your own film to put through the machines !
• What is it you are trying to SAY ? Hmm

What is it you are trying to SAY:

I think I’m trying to say with this project is : Look at what I like doing, isn’t it fun and cool/silly/odd what is to be found ?!  More specifically, to share the preliminary results of my creative research project method. The project I guess is trying to say that it is possible and fun to a embark on an explorative creative process with technology at a low level (and not just use pre-packaged tech things) with some of the wrestling with constraints that that requires. I like that the objects are idiosyncratic, playful compositions but also that they are ornately routed and articulated. I like the message that machines can look different, and be more human and odd ? I guess I’m also trying to have fun with the ideas of usefulness and futility, so it is partially supposed to be humorous? I like the détournement of industrial objects for playful means, the implication that old things can be exciting and that deconstructing a system reveals unexpected inner worlds. I like that the deconstructing of machines is also the deconstructing of how they interact with our world, like the data they save and how they represent our information.

Thinking that Alterity, oddity, idiosyncracy and animism in objects and people and culture I think are totally up there. This was a fascination of my dad’s.

To echo some artists’ quotes that resonate :  “I don’t know what I’m looking for until I see it.” (Cindy Sherman)

“The reason I play so many sounds, maybe it sounds angry, is because I’m trying so many things at one time, you see? I haven’t sorted them out. I have a whole bag of things that I’m trying to work through and get the one essential.” (John Coltrane)

 I want to learn things all the time, I want to understand the patterns behind things. I experience science through craft. With craft I try to cultivate sensitivity in a practiced, purposeful way. If you work with marbling you know just as much about viscosity and flow than a scientist, through your fingertips in a different way. (Tauba Auerbach)

Try shooting some of your own film to put through the machines?

I started thinking about what I would want to film and how. I thought about the beautiful cinematography I appreciate in special films like The Souvenir I & II. I think it would be cool to shoot some video because I spend a lot of time watching videos (not the case for writing because I don’t do enough reading). I thought about recording things I see on commutes, and about the forest walk in Saclay. This has made me consider that what I find interesting about the electronics side is memory, more than just modifying things with math. How the computer represents our world is mainly impacted by its ability to remember it. I’m starting to think that this project could be about memory, putting my own memories into the computer memory. I’m thinking about Iain and Brian’s film Lifesaver and the impact it’s had on me. Also Iain’s photography in general, especially his black and white stage.

I think DRAM board could be a cool project because of how inexpensive large memory is and the memory degradation which could be really poetic in a project about memory. This goes back to Paolo’s suggestion to make a project around an image put into UV erasable EEPROM and watching it slowly degrade in the sun.

I’ve been thinking about how to record as well, with a gopro discretely or with my G2 Cannon more deliberately. I also think that humor should be the primary part of my shooting, not some wanna-be poetic stuff.

**********

Trying to design the interface :

Might need latched buttons like this :

Some all metal heavy duty toggle switches look cool in an array but I’m worried toggle switches will require too much force to turn on and will therefore be annoying all arrayed together on a tiny board.

The other option is to stick with tactile buttons and to convert them into on/off buttons with a JK flipflop. When J and K are pulled high, the outputs Q and !Q toggle every time the clock rises (once per push). This would mean I could have an LED turn on when you push too (helps in the dark for performances!) but I wouldn’t have the pushed-in versus fully extended visual feedback from the button and it would add ICs to my packed board.

I am considering doing this on two boards, the top one would be a single-sided aluminium board which would look cool but also make the top interface more durable. This board would have the leds, keys, JK flip flops. The board below could have lots of space to be laid out in a relaxed, rational way without having to dodge buttons. I could enclose it in a little box or I could leave the two boards exposed on one side or all around.

This follows from the constraint that this will be a real product. I don’t want to make a super difficult to solder and debug highly compact circuit. I want to keep things easy to repair. It also makes the device modular, I could switch a new keyboard and keep the base circuit or vice versa. I would like to keep this device affordable and not using rare / exotic components. I’m more in the robust, standard design world now that Tommy is good at working with perhaps.

*******

I just cleaned by apartment and went through my lab equipment. I will be sending tens of boards and plastic bags to the recycling which makes me sad. I would like to avoid finding myself in this situation in the future.

Check out this Soviet-developed visual programming language DRAKON (https://en.wikipedia.org/wiki/DRAKON)

It would be cool to make a flow diagram like this for the FPGA code I’ve already made.

Also this automation representation called GRAFCET (https://fr.wikipedia.org/wiki/Grafcet)

*******

Check out these user interface principles (https://en.wikipedia.org/wiki/User_interface_design):

• Clarity: the information content is conveyed quickly and accurately.
• Discriminability: the displayed information can be distinguished accurately.
• Conciseness: users are not overloaded with extraneous information.
• Consistency: a unique design, conformity with user’s expectation.
• Detectability: the user’s attention is directed towards information required.
• Legibility: information is easy to read.
• Comprehensibility: the meaning is clearly understandable, unambiguous, interpretable, and recognizable.

********

Just watched a Youtube video by Code Aesthetic called Don’t Write Comments. The implication is that the code should be so readable that you don’t need to comment it. (He organizes code in such a way that the high level architecture comes through and if you want to get into the details you can check out individual functions). I’m trying to do something similar with the interface, have it be directly readable without text just based on color, button size and location.

I like the idea of being more pragmatic with the design and less obsessive about composition. The cut away in the top board could be nice because it show which color bits are going from rpi to the memory.

The question of the colors is tough – RED is for recording ? Should colors follow RGB ? What colors for clock division, and for selecting between MSB and LSB ? What about the LEDs versus the buttons ? EDIT : I’ve sinced moved to greyscale…

****

Being creative in different ways : Apollonian (rational thinking, order, logic, prudence and purity) vs. Dionysian (irrationality, chaos, passion, emotion and instinct). Electronics and logic circuits are clearly Apollonian, and the effects they create on screen are more Dionysian.

****

Looking into code bloat I learned the Unix philosophy of “do one thing and do it well”. Other programming credos :

• less functionality (“worse”) is a preferable option (“better”)’https://en.wikipedia.org/wiki/Worse_is_better)
• “Keep it simple, stupid!” (https://en.wikipedia.org/wiki/KISS_principle)
• rule of least power is a design principle that “suggests choosing the least powerful [computer] language suitable for a given purpose” (https://en.wikipedia.org/wiki/Rule_of_least_power)
• a simple (low complexity) solution to a problem of high complexity is seen as elegant. (https://en.wikipedia.org/wiki/Elegance)

**********

New Prepared Instruments github : https://github.com/preparedinstruments/bechamel

OK, here’s the final version of the boards. I will finally be able to test the one-sided aluminum surface reversed with buttons going through-hole. This is (my first) double-board design, keyboard on one and memory on the other with a ribbon jumping between them. This sampler will have two bits of data for the videos which will be new. Layers will now have different colors associated with them. The gen lock turned out to not be what I thought it was so I’m trying to sync by using V and H syncs (and their inverses) connected to the 590 freq division somehow (either to OE, CLR, or RCLK). I like this new setup to select different bits of the RPI. Cool things here are the double use of the buttons in momentary and latched mode with led indicators. New in this version will also be the triple diode packages for the VGA out.

I’ve taken my favorite interface and mixed it with my favorite circuit, let’s see how it works out ! At least I got to use up a bunch of components I already had lying around. Though, I have to say that no one could pay me enough money to assemble one of these myself, and despite my best efforts it is not minimal and easy to put together. Another issue is the fact that I don’t have the skill of imagining what “customers” want, I seem to be more focused on what I want. Does that make me a wanne-be artist as opposed to a wanna-be designer ?

And some renderings :

**********

Having a think about what my hardware synths could do better than computers. There is the tangible interface, and the speed and fixed-low latency of using hardware to manipulate data instead of software. While I was once again looking into what I can do with a simple FPGA I came across :

• this Elphel NC393 camera device board for handling multiple video streams using an FPGA https://wiki.elphel.com/wiki/File:Nc393-dev-sm.jpeg. Combining multiple video streams, or overlaying, sounds like an application? But in VGA you can do this with just a pot !
• User Jeremy from eevblog’s comment about FLIR explaining that they use FPGAs in order to do “spatial (across pixels) and temporal (across time) filtering simultaneously”.
• video transcoding from one resolution ‘https://en.wikipedia.org/wiki/Transcoding)
• real-time edge detection
• Mister FPGA video game console has a bunch of retro CRT scanline filters here https://boogermann.github.io/Bible_MiSTer/getting-started/extras/video-filters/
• FPGA student projects from this Cornell class : http://people.ece.cornell.edu/land/courses/ece5760/FinalProjects/

********************

I think that this project is becoming about memory, and possibly the parallels between human memory and computer memory. I wonder what role the FPGA would have here. Would it be positioned in between the video input and the memory to act as a kind of variable filter ? I can imagine an interface that would allow you to select between many different filters by moving your hand like on a theremin or an array of trackballs?

*****

Check out this visualization of randomness :

****

First feedback : it needs HDMI – Sam

This Texas Instruments TFP410PAP is back in stock at Mouser and seems easy enough to integrate onto the board at 8euros. It can be controlled without I2C so it could be connected directly to the raspberry pi DEN, HSYNC, VSYNC, color data.  Black Mesa Labs did a board using this IC here : https://blackmesalabs.wordpress.com/2017/12/15/bml-hdmi-video-for-fpgas-over-pmod/

I also found a VGA to HDMI converter on amazon : FOINNEX Adaptateur VGA vers HDMI avec Audio, Convertisseur VGA a HDMI Vieux PC vers TV Moniteur, 1080P VGA to HDMI Adapter pour Anciens Ordinateur 

TI also makes the TFP401x TI PanelBus™ Digital Receiver so I could have HDMI IN and HDMI OUT with the addition of 15 euros of chips…The alternative is to learn to do this with the FPGA.

*****

Check out these snazy metal container for this synth circuit :

https://store.synthrotek.com/Division-6-Business-Card-Synthesizer-PCB-and-IC_p_829.html

Check out this beautiful project Sam sent my by Jurg Lehni which compares different screen technologies : https://juerglehni.com/works/four-transitions

******

Thinking about modularity. If I wanted to have a signal chain with filters etc before the memory. I would need a way of daisy-chaining the power, and a way of patching cables between modules. I want it such that the thing functions with just one module but also can with multiple modules too.

Would the video in/out have to be HDMI to be in line with modern VJ practice ? Found some Chinese chips that do HDMI to VGA like the Lontium LT8511A and the Quintile CH7101B. I guess I would need one of these plus an HDMI out chip for each board for them to be truly modular.

I am thinking right now of a simple custom filter like the one in Photoshop (Nice explanation here : https://ian-albert.com/old/custom_filters/) accomplished with an FPGA and some kind of cool interface (track ball matrix ? capacitive touch array ?) :

***************

Check out this company OKW that makes cool modular knobs just outside of Paris : https://www.okw.fr/fr/Boutons-de-commande

**************

Working with the array of simple, robust, electronic components (switches, knobs, linear pots, track balls, etc.). Trying to think about how they could be daisy-chained together.

****************

Received and soldrerd PCBs !

• The aluminum layer can be engraved ! I could put “bechamel” on it !
• The standoff holes are too small for standard size.
• The boards are not perfectly the same dimensions.
• Perhaps I should have chosen white for the FR4 board instead of green
• No caps on the keyboard board
• Blurg, soldering components on the aluminum board without a heated plate is near impossible. I could have at least selected bigger format ICs.
• The latched keys which are connected to the output buffer enables aren’t really useful. They should be constantly on as the amp can always be just turned down to turn off the channel.

ERRATA MOTHERBOARD :

• From now on I think I will solder with a stencil and an oven, it’s too much work to solder manually.
• The latched keys don’t activate the same channels via buffer that they activate via AND gate to analog switch SEL.
• Also the text BLU, RED etc next to the knobs isn’t really accurate
• Should have VCC and GND on the silkscreen next to keyboard jumper
• Pin 13 and 11 of the 590 should by default be connected together on the next board
• I replaced the caps at the VGA out with 0ohm jumpers because I couldn’t see anything passing through on the oscilloscope
• I should add the turn off switch for rpi
• I am considering getting rid of the integrated rpi, despite its advantages, for a more straightforward HDMI IN or VGA IN. It adds considerable thickness to the board with the bulky 40 pin jumper situation and the fact that it is headless makes debugging a real pain.

ERRATA KEYPAD :

• I’m not sure the idea of using the aluminium sided boards really works, it’s all a bit too risky in terms of short circuits and it’s a real pain to solder (I need a heated plate, a nice microscope, loads of flux and a soldering iron). Fabien’s suggestion is to make the holes larger, so there is little risk of the pins touching the aluminium substrate, and then wiring flexible wire to make the necessary connections. Perhaps add some glue to keep the keys in place and move all the circuitry to the reverse side of the motherboard.
• Fabien had the idea of using the square holes of the mechanical switches possibly to mount them in the metal, perhaps they would even clip into place ?
• I roasted the ICs during soldering I think, the LEDs and JK latches are not working as expected.
• The added height for the two female ribbon cable connectors butting up against each other is insane. If it’s possible to just plug one board directly into the other you can achieve some nice compact sandwich board.
• Once again the 2mm standoff holes are too tiny
• The slot is perfect and the LEDs passing through the holes works as expected (though I should really use insulation on the two legs).

**************

Could I use coils from floppy disk player in a matrix as capacitive touch array ?

Could I make a super low resolution LED monitor to replace the HDMI IN and HDMI OUT DSLR field monitor ? (https://www.amazon.fr/Feelworld-Moniteur-Monitor-1920×1080-Peaking/dp/B07J5C98NW/ref=sr_1_1_sspa?crid=2SJEJTOJ1C6HB&keywords=Cam%C3%A9ra+Moniteur+DSLR&qid=1707557998&s=electronics&sprefix=cam%C3%A9ra+moniteur+dslr+%2Celectronics%2C89&sr=1-1-spons&sp_csd=d2lkZ2V0TmFtZT1zcF9hdGY&psc=1) :

I could also just use the simple rpi 5″ HDMI screen.

Other connection options if I had HDMI out :

Would it be smart to keep a VGA out as a plan B if ever the HDMI stopped working ?

It would be super useful to have a micro usb out to power the portable screen / pico projector. If so not much space left, would need to maybe bring the USB C power cable to the rpi side.

*************

Check out Jim Campbell’s low res display :!

References to reconstructing memories from the mind too !

***************

Setting up another rpi to loop VLC videos. I used primarily this tutorial: https://forums.raspberrypi.com/viewtopic.php?t=17051

First off, I kept the language as english to simplify things (despite having a french keyboard). I believe I did the rpi Lite installation (and then downloaded VLC?) but I’m not 100% sure.

In the place of

nano /home/pi  I have my user name :

nano /home/marrs

I also needed to go to View > Show Hidden to see the .config file then autostart then autovlc.desktop

nano /home/marrs/films/.config/autostart/autovlc.desktop

NOTE : This can’t be a text file, easiest way is to create the file directly in the terminal to avoid any problems as explained here :https://learn.sparkfun.com/tutorials/how-to-run-a-raspberry-pi-program-on-startup/method-2-autostart

I put this in the file (there is nothing else there)

[Desktop Entry] 
Type=Application
Exec=vlc --loop --fullscreen /home/marrs/playlist.m3u

Then control+O to save the file
 I put the m3u playlist here : home/marrs/playlist.m3u

*************

A new vision for this project : it’s a lo-fi device that takes HDMI and outputs HDMI but allows all kinds of very low res transformations like super low resolution GIFs, and saving every Nth frame of a film.

****TESTING ***

• Get sync sorted on this board. **EDIT** Unfortunately taking HSYNC, VSYNC and their inverses, and sending them to the 590 on various pins is not syncing the video. Thinking back, I think I managed this only when I was ANDing a bunch of freq divisions and then inverting the output to record images only every nth frame. *EDIT* OK I’ve got something taking VSYNC as the freq and the AND’ind the outputs to be used to reset the 4040 counters.
• Test the keyboard interface experience. ***EDIT** oof this is painful to do with jumpers and breadboards. Everything seems to be very sensitive to wierdness. It makes me want to eliminate the double board concept and just stick with hard soldered stuff on a single board. In the moments when things were briefly working it was super cool to control things with the keyboard.
• See what other video distortion is possible with the circuit
• I tried out the new HDMI converter, it works well.
• I figured out that you can save a multicolor multichannel image by recording on several channels at once !
• I like the idea of avoiding mission creep – not going into the screen or video codec business but instead staying with the theme of the project : video memory recording and playback.
• I like the idea of emphasizing how little memory there is here (4MB), and how I am trying to use every part of the bison rather than going for more memory.
• the new board should have usb micro female plugs to power an rpi, a VGA to HDMI converter, or the 5″ HDMI screen.
• No more connectors between boards that are mirrored… Thinking of a single-sided board where the buttons relate the the function (latched push button for things that need to be latched like the freq sel) keyboard keys for selecting layers to record to. I thought that having an array of the same button would make things clean but it ends up being confusing what button does what. I like the idiosyncratic and non orthogonal matrix approach.
• Just realized that I only need the single pole analog switch and don’t need the double pole anymore.
• I have higher quality pots I could use for smoother action

Super cool to see everything on the tiny screen actually (but when I plugged in everything from the v synth I think it went above the fuse limit so I’ll have to FIX THIS IN THE NEXT VERSION if I want all to be powered by the board):

*

Trying to make a list of cool new video distortions possible with this board :

• RCK and CLK of 590 could be connected to different frequencies
• could have two different counter pairs for two memories that could be desynchronized

**********

A quick redesign :

• Different components for different functions that they control (flat pots for inputs)
• Added DIP switches to turn on and off diff V SYNC divisions going to 4040 counter reset
• Only two speed buttons now, and they are physically latched
• Nicer quality top facing pots
• HDMI in and out with TI chips
• got rid of some replaceable components
• two micro USB connections to allow for these options :

*****

Trying out some hyper symmetrical design here.

Some considerations :

• Leaving enough room to be able to comfortably twist the knobs
• having mechanic keys close to one another so that they can be easily tapped with adjacent fingers
• associating each key with it’s respective knob spatially and clustering controls that are thematically related (like the dip switch and the two frequency setting pushbuttons which are both temporal)
• components that extend beyond the board on the top and bottom leaving room for hands on the keys and knobs
• Tommy thinks it should be hand held.

And a more controller-like option :

*******

Check out Vincent Rioux’s muq machine and how he show the grid of screen shots :

***

I want to make videos like this guy makes experimental sound sets :

****

I’m going to remake the keyboard board (but on FR4, with connector aligned to motherboard, no latched colors to activate channels) and add the sync lock functionality. This will allow me to finish that project and test it easily.

The videos I have already of the board functioning are cool : diff colors allow for multiple images to share the same frame and be legible. The freeze frame(s) is very cool and being able to freeze different chunks of time I think will add a lot of things to test.

After this board I’ll move back to FPGA as they represent the future of the project I think (also the NO SCHOOL workshop this summer). Before I make I new board I should play more with the FPGA SRAM boards I have already made. Can I , for instance, reproduce the bechamel board with an FPGA? Perhaps it is time to upgrade to an FPGA with more LUTs, even if it is harder to solder in Ball Grid Array packaging (and then why not SRAM in BGA also), and the HDMI helper chips.

The dream would be able to throw 20 of the new boards in the oven and have them all work at the end. I could then send them to friends around the world ! Would be clever to use capacitive touch in this case to avoid needing a physical interface like so : https://github.com/stnolting/captouch.

I could also design a silicone ruber keypad for it ! https://en.wikipedia.org/wiki/Silicone_rubber_keypad

Looks like an ESP32 with SD card can generate video as input, that or a rpi integrated into the board.

This might be one of those “already solved” problems which isn’t that much fun to explore…

***

Next steps for the HX8K board :

1. FFMPEG can output into monob or monow 1 bit pixel format and different dimensions. Test making a low resolution video and putting it on an SD card and having Arduino read it and transfer it to FPGA on the gameboy console board I made. (This will test if can replace rpi or HDMI IN with SD card in on next board)
2. Try again to see if HDMI out is possible with FPGA using the two boards I made to test this. (This will decide if need an HDMI helper chip or not on next board)
3. Try to use internal FPGA BRAM to save a screenshot on the Villette Makerz board. (This will test if need SRAM or not on the next board).
4. Replace mechanical keys with capacitive touch so everything is as light as possible.
5. Plan to get JLC PCB to assemble it ?

****

New top board, no longer aluminum, no more LEDs, which has the V SYNC ADD circuitry, debounced keys, and a female header to connect directly to the motherboard.

*****

Realized that I haven’t used the BRAM on the FPGA and that I could store low res recordings there. *EDIT* But it’s only 64K in total for the HX1K which is very little space. Probably more useful to store a mini buffer before sending it along to the SRAM. I’ve tried to create BRAM primitives in IceCube but it’s not working so far. This code from TinLethax appears to work in IceCube :

module BRAM(
input R_CLK,
input W_CLK,

input [7:0]BRAM_IN,
output reg [7:0]BRAM_OUT,

input [11:0] BRAM_ADDR_R,
input [11:0] BRAM_ADDR_W,

input B_CE_W,
input B_CE_R);

reg [7:0] mem [3003:0];

always@(posedge R_CLK) begin// reading from RAM sync with system clock 
if(!B_CE_R)
    BRAM_OUT <= mem[BRAM_ADDR_R];   
end 

always@(posedge W_CLK) begin// writing to RAM sync with Slave SPI clock.
if(!B_CE_W)
    mem[BRAM_ADDR_W] <= BRAM_IN;
end

endmodule

 module ram (din, addr, write_en, clk, dout);// 512x8
parameter addr_width = 9;
parameter data_width = 8;
input [addr_width-1:0] addr;
input [data_width-1:0] din;
input write_en, clk;
output [data_width-1:0] dout;
reg [data_width-1:0] dout; // Register for output.
reg [data_width-1:0] mem [(1<<addr_width)-1:0];

always @(posedge clk)
begin
if (write_en)
mem[(addr)] <= din;
dout = mem[addr]; // Output register controlled by clock.
end
endmodule 

set_io hdmi_p[0] 139 -io_std SB_LVCMOS
set_io hdmi_p[2] 78 -io_std SB_LVCMOS
set_io hdmi_p[1] 80 -io_std SB_LVCMOS
set_io hdmi_p[3] 137 -io_std SB_LVCMOS

set_io hdmi_n[0] 138 -io_std SB_LVCMOS
set_io hdmi_n[2] 79 -io_std SB_LVCMOS
set_io hdmi_n[1] 81 -io_std SB_LVCMOS
set_io hdmi_n[3] 136 -io_std SB_LVCMOS

set_io clk100 49

`default_nettype none // disable implicit definitions by Verilog
//-----------------------------------------------------------------
// minimalDVID_encoder.vhd : A quick and dirty DVI-D implementation
//
// Author: Mike Field <hamster@snap.net.nz>
//
// DVI-D uses TMDS as the 'on the wire' protocol, where each 8-bit
// value is mapped to one or two 10-bit symbols, depending on how
// many 1s or 0s have been sent. This makes it a DC balanced protocol,
// as a correctly implemented stream will have (almost) an equal
// number of 1s and 0s.
//
// Because of this implementation quite complex. By restricting the
// symbols to a subset of eight symbols, all of which having have
// five ones (and therefore five zeros) this complexity drops away
// leaving a simple implementation. Combined with a DDR register to
// send the symbols the complexity is kept very low.
//-----------------------------------------------------------------

module top(
clk100, hdmi_p, hdmi_n
);

input clk100;
output [3:0] hdmi_p;
output [3:0] hdmi_n;

// For holding the outward bound TMDS symbols in the slow and fast domain
reg [9:0] c0_symbol; reg [9:0] c0_high_speed;
reg [9:0] c1_symbol; reg [9:0] c1_high_speed;
reg [9:0] c2_symbol; reg [9:0] c2_high_speed;
reg [9:0] clk_high_speed;

reg [1:0] c2_output_bits;
reg [1:0] c1_output_bits;
reg [1:0] c0_output_bits;
reg [1:0] clk_output_bits;

wire clk_x5;
reg [2:0] latch_high_speed = 3'b100; // Controlling the transfers into the high speed domain

wire vsync, hsync;
wire [1:0] syncs; // To glue the HSYNC and VSYNC into the control character
assign syncs = {vsync, hsync};

// video structure constants
parameter hpixels = 800; // horizontal pixels per line
parameter vlines = 525; // vertical lines per frame
parameter hpulse = 96; // hsync pulse length
parameter vpulse = 2; // vsync pulse length
parameter hbp = 144; // end of horizontal back porch (96 + 48)
parameter hfp = 784; // beginning of horizontal front porch (800 - 16)
parameter vbp = 35; // end of vertical back porch (2 + 33)
parameter vfp = 515; // beginning of vertical front porch (525 - 10)

// registers for storing the horizontal & vertical counters
reg [9:0] vc;
reg [9:0] hc;
// generate sync pulses (active high)
assign vsync = (vc < vpulse);
assign hsync = (hc < hpulse);

always @(posedge clk_x5) begin
//-------------------------------------------------------------
// Now take the 10-bit words and take it into the high-speed
// clock domain once every five cycles.
//
// Then send out two bits every clock cycle using DDR output
// registers.
//-------------------------------------------------------------
c0_output_bits <= c0_high_speed[1:0];
c1_output_bits <= c1_high_speed[1:0];
c2_output_bits <= c2_high_speed[1:0];
clk_output_bits <= clk_high_speed[1:0];
if (latch_high_speed[2]) begin // pixel clock 25MHz
c0_high_speed <= c0_symbol;
c1_high_speed <= c1_symbol;
c2_high_speed <= c2_symbol;
clk_high_speed <= 10'b0000011111;
latch_high_speed <= 3'b000;
if (hc < hpixels)
hc <= hc + 1;
else
begin
hc <= 0;
if (vc < vlines)
vc <= vc + 1;
else
vc <= 0;
end
end
else begin
c0_high_speed <= {2'b00, c0_high_speed[9:2]};
c1_high_speed <= {2'b00, c1_high_speed[9:2]};
c2_high_speed <= {2'b00, c2_high_speed[9:2]};
clk_high_speed <= {2'b00, clk_high_speed[9:2]};
latch_high_speed <= latch_high_speed + 1'b1;
end
end

always @(*) // display 100% saturation colourbars
begin
// first check if we're within vertical active video range
if (vc >= vbp && vc < vfp)
begin
// now display different colours every 80 pixels
// while we're within the active horizontal range
// -----------------
// display white bar
if (hc >= hbp && hc < (hbp+80))
begin
c2_symbol = 10'b1011110000; // red
c1_symbol = 10'b1011110000; // green
c0_symbol = 10'b1011110000; // blue
end
// display yellow bar
else if (hc >= (hbp+80) && hc < (hbp+160))
begin
c2_symbol = 10'b1011110000; // red
c1_symbol = 10'b1011110000; // green
c0_symbol = 10'b0111110000; // blue
end
// display cyan bar
else if (hc >= (hbp+160) && hc < (hbp+240))
begin
c2_symbol = 10'b0111110000; // red
c1_symbol = 10'b1011110000; // green
c0_symbol = 10'b1011110000; // blue
end
// display green bar
else if (hc >= (hbp+240) && hc < (hbp+320))
begin
c2_symbol = 10'b0111110000; // red
c1_symbol = 10'b1011110000; // green
c0_symbol = 10'b0111110000; // blue
end
// display magenta bar
else if (hc >= (hbp+320) && hc < (hbp+400))
begin
c2_symbol = 10'b1011110000; // red
c1_symbol = 10'b0111110000; // green
c0_symbol = 10'b1011110000; // blue
end
// display red bar
else if (hc >= (hbp+400) && hc < (hbp+480))
begin
c2_symbol = 10'b1011110000; // red
c1_symbol = 10'b0111110000; // green
c0_symbol = 10'b0111110000; // blue
end
// display blue bar
else if (hc >= (hbp+480) && hc < (hbp+560))
begin
c2_symbol = 10'b0111110000; // red
c1_symbol = 10'b0111110000; // green
c0_symbol = 10'b1011110000; // blue
end
// display black bar
else if (hc >= (hbp+560) && hc < hfp)
begin
c2_symbol = 10'b0111110000; // red
c1_symbol = 10'b0111110000; // green
c0_symbol = 10'b0111110000; // blue
end
// we're outside active horizontal range
else
begin
c2_symbol = 10'b1101010100; // red
c1_symbol = 10'b1101010100; // green
//---------------------------------------------
// Channel 0 carries the blue pixels, and also
// includes the HSYNC and VSYNCs during
// the CTL (blanking) periods.
//---------------------------------------------
case (syncs)
2'b00 : c0_symbol = 10'b1101010100;
2'b01 : c0_symbol = 10'b0010101011;
2'b10 : c0_symbol = 10'b0101010100;
default : c0_symbol = 10'b1010101011;
endcase
end
end
// we're outside active vertical range
else
begin
c2_symbol = 10'b1101010100; // red
c1_symbol = 10'b1101010100; // green
//---------------------------------------------
// Channel 0 carries the blue pixels, and also
// includes the HSYNC and VSYNCs during
// the CTL (blanking) periods.
//---------------------------------------------
case (syncs)
2'b00 : c0_symbol = 10'b1101010100;
2'b01 : c0_symbol = 10'b0010101011;
2'b10 : c0_symbol = 10'b0101010100;
default : c0_symbol = 10'b1010101011;
endcase
end
end

// red N
defparam hdmin2.PIN_TYPE = 6'b010000;
defparam hdmin2.IO_STANDARD = "SB_LVCMOS";
SB_IO hdmin2 (
.PACKAGE_PIN (hdmi_n[2]),
.CLOCK_ENABLE (1'b1),
.OUTPUT_CLK (clk_x5),
.OUTPUT_ENABLE (1'b1),
.D_OUT_0 (~c2_output_bits[1]),
.D_OUT_1 (~c2_output_bits[0])
);

// red P
defparam hdmip2.PIN_TYPE = 6'b010000;
defparam hdmip2.IO_STANDARD = "SB_LVCMOS";
SB_IO hdmip2 (
.PACKAGE_PIN (hdmi_p[2]),
.CLOCK_ENABLE (1'b1),
.OUTPUT_CLK (clk_x5),
.OUTPUT_ENABLE (1'b1),
.D_OUT_0 (c2_output_bits[1]),
.D_OUT_1 (c2_output_bits[0])
);

// green N
defparam hdmin1.PIN_TYPE = 6'b010000;
defparam hdmin1.IO_STANDARD = "SB_LVCMOS";
SB_IO hdmin1 (
.PACKAGE_PIN (hdmi_n[1]),
.CLOCK_ENABLE (1'b1),
.OUTPUT_CLK (clk_x5),
.OUTPUT_ENABLE (1'b1),
.D_OUT_0 (~c1_output_bits[1]),
.D_OUT_1 (~c1_output_bits[0])
);

// green P
defparam hdmip1.PIN_TYPE = 6'b010000;
defparam hdmip1.IO_STANDARD = "SB_LVCMOS";
SB_IO hdmip1 (
.PACKAGE_PIN (hdmi_p[1]),
.CLOCK_ENABLE (1'b1),
.OUTPUT_CLK (clk_x5),
.OUTPUT_ENABLE (1'b1),
.D_OUT_0 (c1_output_bits[1]),
.D_OUT_1 (c1_output_bits[0])
);


// blue N
defparam hdmin0.PIN_TYPE = 6'b010000;
defparam hdmin0.IO_STANDARD = "SB_LVCMOS";
SB_IO hdmin0 (
.PACKAGE_PIN (hdmi_n[0]),
.CLOCK_ENABLE (1'b1),
.OUTPUT_CLK (clk_x5),
.OUTPUT_ENABLE (1'b1),
.D_OUT_0 (~c0_output_bits[1]),
.D_OUT_1 (~c0_output_bits[0])
);

// blue P
defparam hdmip0.PIN_TYPE = 6'b010000;
defparam hdmip0.IO_STANDARD = "SB_LVCMOS";
SB_IO hdmip0 (
.PACKAGE_PIN (hdmi_p[0]),
.CLOCK_ENABLE (1'b1),
.OUTPUT_CLK (clk_x5),
.OUTPUT_ENABLE (1'b1),
.D_OUT_0 (c0_output_bits[1]),
.D_OUT_1 (c0_output_bits[0])
);

// clock N
defparam hdmin3.PIN_TYPE = 6'b010000;
defparam hdmin3.IO_STANDARD = "SB_LVCMOS";
SB_IO hdmin3 (
.PACKAGE_PIN (hdmi_n[3]),
.CLOCK_ENABLE (1'b1),
.OUTPUT_CLK (clk_x5),
.OUTPUT_ENABLE (1'b1),
.D_OUT_0 (~clk_output_bits[1]),
.D_OUT_1 (~clk_output_bits[0])
);


// clock P
defparam hdmip3.PIN_TYPE = 6'b010000;
defparam hdmip3.IO_STANDARD = "SB_LVCMOS";
SB_IO hdmip3 (
.PACKAGE_PIN (hdmi_p[3]),
.CLOCK_ENABLE (1'b1),
.OUTPUT_CLK (clk_x5),
.OUTPUT_ENABLE (1'b1),
.D_OUT_0 (clk_output_bits[1]),
.D_OUT_1 (clk_output_bits[0])
);
// D_OUT_0 and D_OUT_1 swapped?
// https://github.com/YosysHQ/yosys/issues/330


SB_PLL40_PAD #(
.FEEDBACK_PATH ("SIMPLE"),
.DIVR (4'b0000),
.DIVF (7'b0001001),
.DIVQ (3'b011),
.FILTER_RANGE (3'b101)
) uut (
.RESETB (1'b1),
.BYPASS (1'b0),
.PACKAGEPIN (clk100),
.PLLOUTGLOBAL (clk_x5) // DVI clock 125MHz
);

endmodule

git clone https://github.com/flashrom/flashrom.git

cd flashrommake

sudo CONFIG_ENABLE_LIBPCI_PROGRAMMERS=no CONFIG_ENABLE_LIBUSB0_PROGRAMMERS=no CONFIG_ENABLE_LIBUSB1_PROGRAMMERS=no install

echo 24 > /sys/class/gpio/export

echo out > /sys/class/gpio/gpio24/direction

flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=20000 -r dump

flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=20000 -w dump

tr '\0' '\377' < /dev/zero | dd bs=2M count=1 of=image
dd if=my_bitstream conv=notrunc of=image

echo 24 > /sys/class/gpio/export

echo out > /sys/class/gpio/gpio24/direction

flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=20000 -w FPGA.bin

echo in > /sys/class/gpio/gpio24/direction

// A nice Azure blue for example :
c2_symbol = 10'b1111010000; // red
c1_symbol = 10'b1011110000; // green
c0_symbol = 10'b1011110000; // blue

c2_symbol = 10'b1111111111; // red
c1_symbol = 10'b1111111111; // green
c0_symbol = 10'b1111111111; // blue

c2_symbol = 10'b0000000000; // red
c1_symbol = 10'b0000000000; // green
c0_symbol = 10'b0000000000; // blue

I have an idea for a next “chapter” in my project : prepared computers or assemblages.

Each computer would be a hodge-podge of different tech from different eras, but would each include some kind of I/O, memory, ALU, and display, cooling. I could return to the e-waste side of things, but still make circuits to control them.

I could use a corps exquis method to combine different types of screens/displays :

• mini CRT
• LCD
• projector
• printer
• e-ink
• galvo lasers

Types of memory :

• floppy
• SRAM
• DDR
• CD
• Tape

ALU :

• FPGA
• microcontroller
• raspberry pi
• mechanical

I/O :

• mouse
• keyboard
• trackball
• touchpad
• speakers
• internet

Cooling

• Peltier
• Fan
• Radiator

The actual functions of the computers would be unclear, they would generate mysterious images and sequences and react to the interface. They would allow me to very clearly be in the practice of making art.

They would highlight what I’ve come to find interesting about the world of computers, the hand-madeness and social dimension of the objects. Each would be unique, idiosyncratic, and I would no longer be in the situation of working with screens and not knowing what exactly the “object” is. The object here would be clear, it would be the computer assemblage. I could revisit my obsession with miniatureness, and oddity in these hybrid “monsters”. They would also require lots of technical challenges to make work, and would not produce waste like the mass production of circuit boards does when making a kit.

This is building on Vivien’s idea to be inspired by full computer builds to emphasize materiality :

It would be really cool to make everything from e-waste, but also to keep the miniature dimensions. It looks like phone screens from Nokia can be controlled by Arduino, but that others are undocumented and hard to control without finding a datasheet :

Some ressources for controlling a TFT display directly with Arduino :

https://community.element14.com/members-area/personalblogs/b/blog/posts/screen-success-hack-like-heck-build-update

Looks like it is doable with a raspberry pi and therefore doable with an FPGA.

None of these will be possible if I don’t have an autonomous board though – one that produces it’s own videos with data (instead of relying on video from a computer or rapsberry pi). So I will have to make this work first, and why not try to have this done for the expo next month in Germany ?

******

This Autonomous board could play videos from memory and display it all on the same board, without any wires !

I am now seeing this as a two board construction. The keyboard is too dense to pack any electronics into really, so it is better just as an interface with a ribbon cable going to the board behind the screen which has the FPGA and microcontroller. The bottom could be in aluminium which would make it stable and could have tabs which bend on the edges. This would provide a solid mounting place for the micrometer knob and the laptop hinge. It would also give a different look to the board as it would be all metal, combining with the micrometer, the screen and the screen hinge to make an all metal looking assemblage.

Not yet sure how to convert the linear motion of the micrometer knob, and I feel that the screen + board might look and be a little top heavy / too thick for the effect.

Check out these beautiful machines from Love Hulten : https://www.lovehulten.com/ Thanks Martin De bie for the ref !

Now I’m thinking it should be flat in fact :

Looking in to TFT LCDs, here’s what I’m finding :

• 40 pins seems to be a kind of standard
• There seems to be at least two modes : ‘RGB’ mode and SPI mode.
• rectangular screens with 800×480 in 4.3″, 5″ or 7″ seems to be standard
• TFTs seem to come with a driver chip like the ILI9341 or the ST7701S
• Some seem to require being initialized by SPI

*****

Kristy has helped me select a nice sized screen, 2.8″ seems to be cute but not trinket-like. Adafruit’s screen sells on Mouser : https://www.adafruit.com/product/1774

It appears to have a simple 8 bit parallel mode by default with a straight-forward timing diagram :

And here’s another explanation of the same thing showing two different options :

The datasheet is detailed and I have Adafruit code to base things on as well.

****

The screen also appears to also have a “raw” Parallel RGB Interface mode which seems to involve the HSYNC, VSYNC, DOTCLOCK, DE, while sending color data to the D pins…..but it looks like first bits (RCM, RIM, and DPI) must be set from the SPI mode ? Also, it looks like you have to calculate yourself the timings of the screen based on the clock and screen dimensions (and also set these bits (DIV, RTN, etc.) ? But it looks super simple afterward :

*************

PROJECT UPDATE :

This project seems to be unlucky :

• My Mouser order was stolen from inside my building or was never actually delivered.
• The idea of having doublesided PCB + aluminum went out the window when I saw the cost (approx. 10x a normal PCB)
• The replacement screen I ordered from Amazon has only 20 connections (instead of 50) and only allows SPI, which is very difficult for the FPGA to do and so would require a microchip + FPGA teamwork which seems technically a real headache.
• Currently the HX4K is not starting up, despite having both PLLs connected now. I’m not sure what I’m missing but it is different enough from the HX1K to merit more research before using I guess.

On the other hand I have been preparing for my ESDAC creative coding class and enjoying learning about the different kinds of P5JS codes that exist. I made an image to show the typologies I found so far :

I should also have a class on Glitching !!! And on WEBGL Shader, check out this awesome book : https://thebookofshaders.com/03/

Moiré

Field

Random walk

Spirograph

Cavegen

Radial

Hyper-realistic face generation

**********

Trying to put together an analysis of the kind of hardware effects I have been producing so far :

Here is a slide trying to show the process of designing a board :

And some sketches of circuits I’ve made over the course of the project :

****

Older board I never photographed :

****

I finally have access to opencores.org ! Some things of interest so far :

• Math – https://opencores.org/projects/verilog_fixed_point_math_library
• Noise and PRNG  – https://opencores.org/projects/gng
• CORDIC core (for trig functions) – https://opencores.org/projects/verilog_cordic_core
• ATTINY core – https://opencores.org/projects/attiny_atmega_xmega_core

There is plenty more, like H.264 and JPEG decoding, SoC, sorting algorithms, DDR controllers, Real-time clocks, PCI bus controllers, DSP Filters, SD card controllers, SPI/UART/USB/I2C etc interfaces, etc.

****

Some aesthetic references I was reminded of this week :

• The fractal, “trippy”, spaceship-like camera movements, and kaleidescopic winamp visuals : https://www.youtube.com/watch?v=RBkhUg1oVIE

• The black and white retro dithering from Return Of The Obra Dinn https://www.youtube.com/watch?v=k2y5qH2Jn14
• 

*************

Post Darmstadt workshop thoughts :

• CNC building workshops are hard. In the Fab Academy it takes an entire team two weeks. My two attempts, a while back at CMU and in Germany this week were too ambitious. If I want to have everyone leave with a working machine I need to do a lot of prep before hand. This weekend I could have 3D printed parts before hand that clipped together in the spirit of my linear actuators for the Fab Ac (https://www.marrs.io/medium-sized-cnc-foam-cutter-with-leon-reboul/). Alternatively I could have bought a cheap drawing kit from Aliexpress for around 100 euros if I had gotten myself organized early enough. I think threaded rods may also be a better solution than belt drives which require more skill to design with. The linear rails were cool but they required special low-profile screws so the students struggled a bit with this. It also seems to be the case that servos can simply replace all the challenges of stepper motors requiring drivers for everyone but experts. Essentially : Don’t overthink it, do the most obvious tech thing that is the shortest path for beginners. This will be my strategy for the Beaux Arts workshop coming up where I’ll focus on servos only.
• I should probably keep in mind the challenge of the workshop. The higher the challenge for the participants, the more work I need to do to prepare everything. More plug and play = less challenge.
• Learning to be a free lancer will take time but I need to consider myself as a professional, not doing things on a shoestring budget and exhausting myself. As I move around and workshop in different places, I need to keep in mind my audience – engineering students are different from artists, designers, enthusiasts and kids.
• It might be cool to learn to make video PDFs for future presentations when talking about video synthesis. Also maybe live coding with toy shader / P5JS to illustrate things ?
• For the expo, I was happy to have a plug and play FPGA solution that just generated images. The boards I have made that record video all need heavy intervention on the part of the player and are not intuitive at all. I am still hoping to find a way to order the remaining parts from Mouser soon so I can test SD card reading and FPGA screen displaying.
• For my talk, I still don’t have a way of directly connecting my earlier projects with the new video synth project.

Next steps :

I am feeling positively about just following my interests, and not necessarily knowing where I am going with this project. I want to :

• make abstract generating form code with FPGA using the new trig functions, multiplication and division from opencores !
• experiment with more filters using the FPGA.
• move beyond my current aesthetic, which will require making the recorded image not jump around. I should be able to do this pretty easily when the FPGA is sending the sync signals.

*************

Post BA workshop thoughts :

• The students this time were really into following a more formal series of prepared slides with exercises, and seemed less interested in building their own drawing machines. The Arduino exercises were well received, as well as the glitch exercise, and also the soldering workshop. I like that they bring their own projects and integrate them.
• I tried to be extra professional this time, staying late with students to continue helping them, being extra careful to put everything back in its proper place, and generally being as uncompromising as possible in the quality I’m trying to bring to the workshop.
• My little polyphonic synth, portable speaker, and VGA arduino board were a good thing to bring. I should have something interactive that puts images on the screen I think and a lamp to show off the solar sunflower too.
• I had too many projects to manage in parallel at one point and was rushing about everywhere. Not sure what the solution is there, there were around 8/9 people for the first two days.
• We need some basic boards like mic amp, speaker amp, easy stepper motor drivers, relay boards, etc. that are useful at the BD.
• Vincent was suggesting that we think of ways of creating a virtual expo space for digital works somehow in relation to his radio station at the school which is appreciated.

*************

Post website being down, looking at previous pages now and having some perspective thoughts :

• pure p5js coding I find far less exciting than hardware visual effects, it’s all too immediate and mediated. It’s not raw and unstable like analogue. I think I’m more convinced that the painful process of doing simple things the hardest way possible is actually productive creatively for the friction it affords.
• Putting a series of bitmaps on an SD card (possibly with a custom FFMPEG running on raspberry pi) and then onto the screen would be cool. The idea for a custom FFMPEG comes from this tutorial http://dranger.com/ffmpeg/tutorial01.html which I found here https://github.com/codecrafters-io/build-your-own-x which I in turn found on reddit FREE MEDIA HECK YES 
• I need to get the sync working to test some other (less jarring) visual experiences.
• The Real Time Corrupter methods (piping, etc.) are brilliant and I have to copy them to experiment with FPGA memory filters. Beyond the RTC it would be very cool to experiment with DCT compression filter spectra.
• I don’t think I need to look under each hole and check under each rock. Getting one type of memory working, and one video protocol, is good enough and I don’t need to suffer with DDR and HDMI in this way of working I’m assuming currently.
• For marketing video synths, there is the website php like Marc did (https://muca.cc/fr) or the instagram/facebook marketplace option. Alternatively there are services that host the payment side of things like gumroad, prestashop, and wordpress https://wordpress.com/fr/ecommerce/
• I’m doing NO SCHOOL this summer !! Planning on getting a simple FPGA v synth programmable with Arduino / RPI in python and made on an aluminum-backed board (with SMD VGA).

*************

Learned about live coding with hydra :

I will be VJing this month, we’ll see what that experience is like. Perhaps it will help me design boards that VJs could use. Here’s what I learned :

• The stress of doing a live performance when everything isn’t set up and rehearsed many times before hand is high. One would need to have a bunch of backups, and a very rehearsed performance to lower stress.
• Having a small lamp is helpful to see what connections and knobs you are messing with
• One question is how to react to music, does a beat equal a varying of a parameter ? How to react to song changes ?
• How should “effects” be introduced ? I defaulted towards starting simple and then going towards the more complex effects
• Clearly having performance grade equipment means everything is super robust, easy to use, etc. This makes me think that it would make sense to make a really reliable simple filter, for instance. This also connects with a larger issue for me : I want to do things differently but there are often good reasons why things are done a particular way…
• Sending my crazy VGA to a machine that digitizes it and sends it on as HDMI is probably safer than directly sending things to the projector…

I want to use an older media device (cassette tape, floppy, mini-VHS?) in my next board. I realized that if my practice is about “doing things the hard way”, that should be visually communicated in the design (no one understands if the electronics are done the hard way or not…). This would also signal that I am not trying to make cutting edge new things but that my interests are elsewhere.

Here is a first look at some video synth companies and their designs :

Trying again with the floppy drive :

Check out this video extracting motion from video by just inverting and sliding videos sideways :

****************

I finally bought preparedinstruments.com ! Here are some potential designs for the page :

Making a simple FPGA video synth for PEW 2023 at Villette Makerz. It takes audio in and generates patterns based on the voltage threshold and the 9 keys being pressed.

The code is here : https://github.com/merlinmarrs/iCE40HX-verilog-video-patterns

This time the top interface side has only buttons and no electronics. I have a simplified VGA out and HDMI with the correct LVDS resistor setup this time. I am relying on raspberry pi or arduino for programming.

Trying a grid ground pour on the Stop layer :

Here’s the final soldered version :

Nicer photos :

Found a site called OpenCores (https://opencores.org) that has free FPGA IP like math libraries.

Here are some tests with cool looking patterns :

Because dividing, trig functions, etc. aren’t supported by default, the most promising is the bitwise boolean logic operating on the entire vector :

wire[11:0] bit_or;
assign bit_or = h_count[11:0] | v_count[11:0];

[...]

if (bit_or[5] == 1 | bit_or[3] == 0) begin

wire[11:0] bit_xor;
assign bit_xor = h_count[11:0]^v_count[11:0];

[...]

if (bit_xor[2] == 1 | bit_xor[4] == 1) begin

wire[11:0] bit_and;
assign bit_and = h_count[11:0]&v_count[11:0];

...

if (bit_and[6] == 1 | bit_xor[7] == 1) begin

I could imagine having the keys vary which logic operations are in play and having the music threshold change the color of the pixels for instance.

***

This site has a module for a quasi random number generator : https://simplefpga.blogspot.com/2013/02/random-number-generator-in-verilog-fpga.html

This site has some good Processing examples : http://www.generative-gestaltung.de/2/

***

If I do this workshop again I’d like to design it to be made on aluminum as, it is at least in principle, recyclable.

PCBWay’s diagram of a double layer board (https://www.pcbway.fr/pcb_prototype/General_introduction_of_Aluminum_PCB.html) :

***

Simplest imaginable keypad switch (and audio in post comparator) test works :

module top (
input hwclk,
output led1,
input keypad_c1
);

assign led1=keypad_c1;

endmodule

`default_nettype none

module LFSR (
input clock,
input reset,
output [12:0] rnd
);

wire feedback;
reg [12:0] random, random_done;
reg [3:0] count; //to keep track of the shifts

assign feedback = random[12] ^ random[3] ^ random[2] ^ random[0];
assign rnd = random_done;
always @ (posedge clock)
begin
if (reset)
begin
random <= 13'hF; //An LFSR cannot have an all 0 state, thus reset to FF
count <= 0;
end

else
begin
if (count == 13)
begin
count <= 0;
random_done <= random; //assign the random number to output after 13 shifts
end

else
begin
random <= {random[11:0], feedback}; //shift left the xor'd every posedge clock
count <= count + 1;
end
end
end
endmodule

wire [12:0] random_number;

[...]

LFSR random_s(
.clock(clk_in),
.reset(reset),
.rnd(random_number)
);

`default_nettype none
module tempo(
input wire clk,
output reg half_sec_pulse
);

reg[25:0] div_cntr1;
reg[25:0] div_cntr2;
always@(posedge clk)
begin
div_cntr1 <= div_cntr1 + 1;
if (div_cntr1 == 0)
if (div_cntr2 == 0)
begin
div_cntr2 <= 0;
half_sec_pulse <= ~half_sec_pulse;
end

else
div_cntr2 <= div_cntr2 + 1;
else
half_sec_pulse <= half_sec_pulse;
end

endmodule

`default_nettype none

module vga_sync_test(

input wire clk_in,
input wire reset,
input wire key[8:0],
input wire adc_in,
output reg led_red,
output reg led_green,

//VGA OUT

output reg [3:0] r_out,
output reg [3:0] b_out,
output reg [3:0] g_out,
output wire h_sync,
output wire v_sync

);

wire half_sec;
wire [12:0] random_number_0;
wire [12:0] random_number_1;
wire [12:0] random_number_2;
wire [12:0] random_number_3;
wire [12:0] random_number_4;
wire [12:0] random_number_5;
wire [12:0] random_number_6;
wire [12:0] random_number_7;
wire [12:0] random_number_8;
wire [12:0] random_number_9;
wire [7:0] sine_wave;
wire display_en;
wire [11:0] h_count;
wire [11:0] v_count;

localparam h_pixel_max = 1280;
localparam v_pixel_max = 960;
localparam h_pixel_half = 640;
localparam v_pixel_half = 480;
localparam h_pixel_25 = 320;
localparam v_pixel_25 = 240;
localparam h_pixel_75 = 960;
localparam v_pixel_75 = 700;

//VGA COLOR OUT

always @(posedge clk_in) begin

if (display_en) begin

if ( key[0] == 0 &&

h_count < h_pixel_25 + random_number_1[4:0] && v_count < v_pixel_25 + random_number_7[8:5] &&
h_count > h_pixel_25 - random_number_2[4:0] && v_count > v_pixel_25 - random_number_2[8:5]

) begin

r_out <= random_number_1[3:0];
g_out <= random_number_5[3:0];
b_out <= random_number_9[6:4];

led_green <= 1;

end

else if ( key[1] == 0 &&

h_count < h_pixel_half + random_number_7[5:0] && v_count < v_pixel_half + random_number_7[10:5] &&
h_count > h_pixel_25 - random_number_6[5:0] && v_count > v_pixel_25 - random_number_6[10:5]

) begin

r_out <= random_number_3[7:5];
g_out <= random_number_3[3:0];
b_out <= random_number_6[6:4];

led_green <= 1;

end

else if ( key[2] == 0 &&

h_count < h_pixel_25 + random_number_8[6:0] && v_count < v_pixel_25 + random_number_8[12:6] &&
h_count > h_pixel_half - random_number_9[6:0] && v_count > v_pixel_half - random_number_9[11:5]

) begin

r_out <= random_number_4[7:5];
g_out <= random_number_5[3:0];
b_out <= random_number_7[6:4];
led_green <= 1;

end

else if ( key[3] == 0 &&

h_count < h_pixel_half + random_number_0[7:0] && v_count < v_pixel_half + random_number_0[7:0] &&
h_count > h_pixel_half - random_number_3[7:0] && v_count > v_pixel_half - random_number_3[11:4]

) begin

r_out <= random_number_8[7:5];
g_out <= random_number_8[3:0];
b_out <= random_number_8[6:4];
led_green <= 1;

end

else if ( key[4] == 0 &&

h_count < h_pixel_75 + random_number_2[8:0] && v_count < v_pixel_half + random_number_2[11:3] &&
h_count > h_pixel_75 - random_number_4[8:0] && v_count > v_pixel_half - random_number_4[11:3]

) begin

r_out <= random_number_7[7:5];
g_out <= random_number_7[3:0];
b_out <= random_number_7[6:4];

led_green <= 1;

end

else if ( key[5] == 0 &&
h_count < h_pixel_half + random_number_3[9:0] && v_count < v_pixel_75 + random_number_3[11:2] &&
h_count > h_pixel_half - random_number_8[9:0] && v_count > v_pixel_75 - random_number_8[11:2]

) begin

r_out <= random_number_5[7:5];
g_out <= random_number_5[3:0];
b_out <= random_number_5[6:4];
led_green <= 1;

end

else if ( key[6] == 0 &&

h_count < h_pixel_75 + random_number_4[10:0] && v_count < v_pixel_75 + random_number_4[11:1] &&
h_count > h_pixel_75 - random_number_6[10:0] && v_count > v_pixel_75 - random_number_6[11:1]

) begin
r_out <= random_number_4[7:5];
g_out <= random_number_4[3:0];
b_out <= random_number_4[6:4];
led_green <= 1;
end
else begin
r_out <= random_number_2[3:0];
g_out <= random_number_3[6:4];
b_out <= random_number_4[3:0];
led_green <= 0;
end
end
else begin
r_out <= 4'b0000;
g_out <= 4'b0000;
b_out <= 4'b0000;
led_green <= 0;
end
end

vga_sync vga_s(

.clk_in(clk_in),
.reset(reset),
.h_sync(h_sync),
.v_sync(v_sync),
.h_count(h_count),
.v_count(v_count),

.display_en(display_en) // '1' => pixel region

);

LFSR random_s(

.clock(clk_in),
.reset(reset),
.half_sec_pulse(half_sec),
.rnd_0(random_number_0),
.rnd_1(random_number_1),
.rnd_2(random_number_2),
.rnd_3(random_number_3),
.rnd_4(random_number_4),
.rnd_5(random_number_5),
.rnd_6(random_number_6),
.rnd_7(random_number_7),
.rnd_8(random_number_8),
.rnd_9(random_number_9)
);

sine_wave_gen sine_wave_s(
.clk(clk_in),
.data_out(sine_wave)
);

tempo tempo_s(
.clk(clk_in),
.half_sec_pulse(half_sec)
);

endmodule

set_io v_sync 97
set_io h_sync 76
set_io clk_in 49
set_io reset 66

set_io r_out[0] 91
set_io r_out[1] 95
set_io r_out[2] 96

set_io g_out[0] 75
set_io g_out[1] 74
set_io g_out[2] 73

set_io b_out[0] 87
set_io b_out[1] 88
set_io b_out[2] 90

set_io key[0] 37
set_io key[1] 38
set_io key[2] 39
set_io key[3] 41
set_io key[4] 42
set_io key[5] 43
set_io key[6] 44
set_io key[7] 45
set_io key[8] 47
set_io led_red 23
set_io led_green 24
set_io adc_in 56

/*
 * Created by ArduinoGetStarted.com
 *
 * This example code is in the public domain
 *
 * Tutorial page: https://arduinogetstarted.com/reference/library/arduino-file.readbytes
 */


#include <SD.h>


#define PIN_SPI_CS 4


File file;
char buf[200];


void setup() {
  Serial.begin(9600);
  DDRD = B11111111;


  if (!SD.begin(PIN_SPI_CS)) {
    Serial.println(F("SD CARD FAILED, OR NOT PRESENT!"));
    while (1); // don't do anything more:
  }


  // open file for reading
  file = SD.open("albers.hex", FILE_READ);
  if (file) {
    int avail_len = file.available();
    int read_len = file.readBytes(buf, avail_len); // read all to buffer to buffer


    Serial.print("Length:");
    Serial.println(read_len);
    Serial.println("Content:");


              for (int i=0; i<200; i++) {
   
    Serial.print(byte(buf[i]));
    PORTD = byte(buf[i]);
          }
   


    file.close();
  } else {
    Serial.print(F("SD Card: error on opening file"));
  }
}


void loop() {
}

`default_nettype none

module vga_sync_test(

input wire clk_in,
input wire reset,

input wire rec, // Direction of io, 1 = set output, 0 = read input

//RASPBERRY PI
input wire [3:0] r_in,
input wire [3:0] b_in,
input wire [3:0] g_in,

//VGA OUT
output reg [3:0] r_out,
output reg [3:0] b_out,
output reg [3:0] g_out,

output wire h_sync,
output wire v_sync,

//SRAM

output reg [20:0] addr,
inout wire [7:0] io, // inout must be type wire

output wire cs_1,
output wire cs_0,
output reg we_0

);


wire half_sec;

wire [12:0] random_number_0;
wire [12:0] random_number_1;
wire [12:0] random_number_2;
wire [12:0] random_number_3;
wire [12:0] random_number_4;
wire [12:0] random_number_5;
wire [12:0] random_number_6;
wire [12:0] random_number_7;
wire [12:0] random_number_8;
wire [12:0] random_number_9;
wire [7:0] sine_wave;

wire [7:0] data_in;
wire [7:0] data_out;

reg toggle;

reg [7:0] a, b;

assign io = rec ? a : 8'bzzzzzzzz;

assign data_out = b;

assign data_in[1:0] = r_in[3:2];
assign data_in[3:2] = b_in[3:2];
assign data_in[5:4] = g_in[3:2];
assign data_in[7:6] = 2'b00;

wire display_en;
wire [11:0] h_count;
wire [11:0] v_count;

localparam h_pixel_max = 1280;
localparam v_pixel_max = 960;
localparam h_pixel_half = 640;
localparam v_pixel_half = 480;


reg [1:0] count2; //to keep track of the shifts

wire [11:0] bit_or;
assign bit_or = h_count[11:0]|v_count[11:0];

wire [11:0] bit_xor;
assign bit_xor = h_count[11:0]^v_count[11:0];

wire [11:0] bit_and;
assign bit_and = h_count[11:0]&v_count[11:0];

wire [11:0] bit_nand;
assign bit_nand = h_count[11:0]& ~v_count[11:0];

wire [11:0] bit_xnor;
assign bit_xnor = h_count[11:0]^ ~v_count[11:0];

reg [11:0] out_bit ;


// CS: low to select, high to deselect

assign cs_0 = toggle ? 1 : 0;
assign cs_1 = toggle ? 0 : 1;

//SRAM address counter

always @(posedge clk_in) begin

if (addr == 0) begin
toggle <= toggle+1;
end

if (reset) begin
addr <= 0;
end else begin
addr <= addr+1;

end
end


//REC control

always @(posedge clk_in) begin

b <= io;
a <= data_in;

if (rec) begin
we_0 <= addr[0]; //not sure why it isn't the inverse of addr[0] but that doesn't make the inverse on 'scope
end
else begin
we_0 <= 1;
end
end

//VGA COLOR OUT

always @(posedge clk_in) begin

case(count2)
2'b00: out_bit = bit_or;
2'b01: out_bit = bit_xor;
2'b10: out_bit = bit_and;
2'b11: out_bit = bit_nand;

default: out_bit = bit_xnor;
endcase
count2 <= count2 + 1;
end

//VGA COLOR OUT

always @(posedge clk_in) begin
if (display_en) begin

if (out_bit[random_number_2[3:0]] == 1 | out_bit[random_number_6[3:0]] == 0) begin

r_out <= random_number_2[3:0];
g_out <= random_number_3[3:0];
b_out <= random_number_4[3:0];

end

else begin

r_out[3:2] <= data_out[1:0];
r_out[1:0] <= data_out[1:0];
g_out[3:2] <= data_out[3:2];
g_out[1:0] <= data_out[3:2];
b_out[3:2] <= data_out[5:4];
b_out[1:0] <= data_out[5:4];

end

end else begin

r_out <= 4'b0000;
g_out <= 4'b0000;
b_out <= 4'b0000;

end
end

vga_sync vga_s(
.clk_in(clk_in),
.reset(reset),
.h_sync(h_sync),
.v_sync(v_sync),
.h_count(h_count),
.v_count(v_count),
.display_en(display_en) // '1' => pixel region
);

LFSR random_s(
.clock(clk_in),
.reset(reset),
.half_sec_pulse(half_sec),
.rnd_0(random_number_0),
.rnd_1(random_number_1),
.rnd_2(random_number_2),
.rnd_3(random_number_3),
.rnd_4(random_number_4),
.rnd_5(random_number_5),
.rnd_6(random_number_6),
.rnd_7(random_number_7),
.rnd_8(random_number_8),
.rnd_9(random_number_9)
);

sine_wave_gen sine_wave_s(
.clk(clk_in),
.data_out(sine_wave)
);

tempo tempo_s(
.clk(clk_in),
.half_sec_pulse(half_sec)
);

endmodule

FPGA SRAM board

Shadertoy is the future of this project, so what am I doing ? This new board is a reprogrammable FPGA 2D pixel shader (aka fragment shader) which can control the color of pixels and know only of the coordinate of the pixel being drawn. Pixel shaders can also sample the values of nearby pixels. As a result, they can do 2D post-processing (https://en.wikipedia.org/wiki/Video_post-processing) or filtering for a video streams. Why do this on an FPGA rather than in-brower ? You are super low level, and you have constraints based on the number of LUTs, it has a live-playable interface. In any case, I think this is my last board for a while, unless I can make an AI board somehow.

On the other hand, I’m not sure how profound it is to make photoshop like filters. (You can test a 5×5 grid if you go under Filters>Custom in PS). They are all kind of superficial…

I am starting to realize that I spend loads of time debugging soldering errors (yes, I get the learning that comes with that but still). If I made boards and had them assembled elsewhere I would not have this issue. Should I also, in the same spirit, just jump ahead to what everyone else is doing, with the thinking that they are not wasting time on problems that have already been solved and are exploring an interesting space.

I also spend a lot of time designing and building boards, interfaces, and less time programming them: the SCARA robot arm that I didn’t even plug in, the covid temperature interface board, the drone, and the MIT version of the mini swarm robot. On the other side are the projects I’ve perhaps spent too must time making and incrementally remaking perhaps : 3105 power harvester + radio transciever, the Ben Eater style memory. A nice balance was perhaps the solar sunflower protytpes which were experiments with form and function.

*EDIT* I am now thinking that I must work on things that would be of interest to other people, like Machine Learning for instance. I must be humble, just because something is interesting to me doesn’t mean anyone else cares ! Turns our that FPGAs consume a lot less current than GPUs so they are not bad for implementing ML once the training is done. Here is a info about ML with FPGAs :

• https://www.youtube.com/@marcowinzker3682
• https://www.mdpi.com/2076-3417/12/1/89
• https://github.com/verimake-team/MLonFPGA
• https://qengineering.eu/deep-learning-with-fpga-aka-bnn.html
• https://qengineering.eu/embedded-vision.html#FPGA_stitching

Great post about the marble machine project : https://www.reddit.com/r/MarbleMachineX/comments/pzh5kw/an_open_letter_to_martin_on_the_state_of_the/

• The machine is not about reliability and precision, it is about imperfection and the journey
• It’s an art project, it is a project for the project’s sake and the documentation.
• The project shouldn’t run like a start-up, and we are not the sum of what we produce for capitalism
• Not specializing in one thing is what makes this project cool.

ERRATA :

• I think the 590 is not clock dividing as expected…Is it not 3.3V compatible ? I think so, even though unclear on Mouser website.
• Currently only 2 bits of each raspberry pi color input are appearing despite having selected dpi24 in the rpi config file.
• The fine pots are the wrong footprint for the pots I have.
• I could have used DEN (display enable) from the raspi.
• sometimes the rpi starts up and then restarts after playing only a few seconds of video…not sure why.

To change the PLL, there is a tool in IceCube2 under Tool>Configure>Configure PLL Module

Here is the user guide explaining how to use it : https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/IK2/FPGA-TN-02052-1-4-iCE40-sysCLOCK-PLL-Design-User-Guide.ashx?document_id=47778

I want the following options :

• General Purpose I/O Pad or Core Logic
• Using a feedback path internal to the PLL
• Input Frequency (MHz) : 100
• Output Frequency (MHz) : 25
  

Here is the new PCF file :

set_io v_sync 87
set_io h_sync 88
set_io clk_in 64
set_io reset 66
set_io r0 81
set_io r1 80
set_io r2 79
set_io g0 94
set_io g1 93
set_io g2 91
set_io b0 76
set_io b1 75
set_io b2 74
set_io led 45
set_io locked_led 37

I made a pcf to go with this test code :

set_io R7IN 107
set_io R6IN 106
set_io R5IN 105
set_io R4IN 104
set_io G7IN 97
set_io G6IN 96
set_io G5IN 95
set_io G4IN 112
set_io B7IN 102
set_io B6IN 101
set_io B5IN 99
set_io B4IN 98
set_io R7OUT 81
set_io R6OUT 80
set_io R5OUT 79
set_io R4OUT 78
set_io G7OUT 94
set_io G6OUT 93
set_io G5OUT 91
set_io G4OUT 90
set_io B7OUT 76
set_io B6OUT 75
set_io B5OUT 74
set_io B4OUT 73

set_io v_sync 87
set_io h_sync 88
set_io clk_in 64
set_io reset 66
set_io r0 81
set_io r1 80
set_io r2 79
set_io g0 94
set_io g1 93
set_io g2 91
set_io b0 76
set_io b1 75
set_io b2 74

set_io io0 1
set_io io1 2
set_io io2 3
set_io io3 4
set_io io4 122
set_io io5 121
set_io io6 120
set_io io7 119

set_io a0 138
set_io a1 139
set_io a2 141
set_io a3 142
set_io a4 143
set_io a5 8
set_io a6 9
set_io a7 10
set_io a8 11
set_io a9 12
set_io a10 136
set_io a11 135
set_io a12 134
set_io a13 129
set_io a14 128
set_io a15 117
set_io a16 116
set_io a17 115
set_io a18 114
set_io a19 137
set_io a20 113

set_io cs1 71
set_io we0 7

Here are some images of what a new device could look like !

What about an FPGA chip holder ? And a snazzy pivotable SD card holder ? Using meanders this time? With its own fictional programming language like in that assembly video game ? With a mini PCI-E connector somewhere ?

To pre-digest the videos for the FPGA before putting them on a gigantic SD card, I could use ffmpeg to output a less compressed format like .avi or an .mkv and then erase the header and footer ?

Have a name (little Lebowski urban achiever is too long), and a format 100×80 (free Eagle max), and a rough layout (HDMI super close, USB next to FTDI and to flash memory, all the memory to the right equidistant to the chip). AND, some kind of transparent cover, a first for me, make it seem more like a legitimate product and would reduce the risk of short circuits from something conductive falling on the board. For the symbols on the keyboard, there is the Comodore 64 keyboard symbol set which is cool. Or some ancient symbols ??

I am now moving away from SDRAM, challenging and I’m not sure why I’m putting myself through it. The real interest is going to be decoding videos stored on the SD card and putting them on screen. I want to try to do it like the pros – drawing to the screen in the blanking period and using only one SRAM.

****

Still trying to resolve the A18 issue.

• I tried soldering another IO pin to pin 20, but this led to total chaos, none of the address pins working. I could have tried severing the link between the pin 20 and the SRAM but I don’t want to damage the board before I identify the problem (it may be in the code?).
• Trying to lower the size of the address counter to stop at 17 instead of going to 18.
• I connected to the rpi’s DEN and changed the code to work with it instead of the FPGAs display en (it doesn’t work anyways). It is cool as it is more likely to capture the image on the rpi if I understand correctly.

****

I am now trying some of the code I was dreaming about – modifying the input and output video stream based on other parallel data.

Here is one strategy based on two bits of the same color having an impact on recording and playback.

if (b[3]==b[2]) begin
a <= data_in;
end
else begin
a <= 8'b00000000;
end

I have the two memories working (excepted A18 on the second SRAM), and also tried reading DEN from the rpi. It makes some pretty funky glitches by touching the RAM pins with my hands !

Also check out the bitmap to program the FPGA :

`default_nettype none

module vga_sync_test(

input wire clk_in,
input wire reset,

input wire rec, // Direction of io, 1 = set output, 0 = read input

//RASPBERRY PI
input wire [3:0] r_in,
input wire [3:0] b_in,
input wire [3:0] g_in,
input wire DEN, // I SOLDERED A WIRE HERE TO ACCESS DEN ON THE RPI !!

//VGA OUT
output reg [3:0] r_out,
output reg [3:0] b_out,
output reg [3:0] g_out,

output wire h_sync,
output wire v_sync,

//SRAM

output reg [20:0] addr,
output reg [20:0] addr_copy,
inout wire [15:0] io, // inout must be type wire

output wire cs_3,
output wire cs_2,
output wire cs_1,
output wire cs_0,

output reg we_1,
output reg we_0

);

wire [15:0] data_in;
wire [15:0] data_out;

reg [1:0] toggle;

reg [15:0] a, b;

assign io = rec ? a : 16'bzzzzzzzzzzzzzzzz;

assign data_out = b;

assign data_in[1:0] = DEN ? r_in[3:2] : 0; // I SOLDERED A WIRE HERE TO ACCESS DEN ON THE RPI !!
assign data_in[3:2] = DEN ? b_in[3:2] : 0; // I SOLDERED A WIRE HERE TO ACCESS DEN ON THE RPI !!
assign data_in[5:4] = DEN ? g_in[3:2] : 0; // I SOLDERED A WIRE HERE TO ACCESS DEN ON THE RPI !!
assign data_in[7:6] = 2'b00;

assign data_in[9:8] = DEN ? r_in[3:2] : 0;
assign data_in[11:10] = DEN ? b_in[3:2] : 0;
assign data_in[13:12] = DEN ? g_in[3:2] : 0;
assign data_in[15:14] = 2'b00;

wire display_en;
wire [11:0] h_count;
wire [11:0] v_count;

localparam h_pixel_max = 1280;
localparam v_pixel_max = 960;
localparam h_pixel_half = 640;
localparam v_pixel_half = 480;

// CS: low to select, high to deselect

assign cs_0 = toggle == 2'b00 ? 1 : 0;
assign cs_1 = toggle == 2'b01 ? 1 : 0;
assign cs_2 = toggle == 2'b10 ? 1 : 0;
assign cs_3 = toggle == 2'b11 ? 1 : 0;

//SRAM address counter

always @(posedge clk_in) begin

if (addr == 0) begin
   toggle <= toggle+1;
end

if (reset) begin
   addr <= 0;
end else begin
   addr <= addr+1;
   addr_copy <= addr_copy+1;

end
end

//REC control

always @(posedge clk_in) begin

   b <= io;
   a <= data_in;
if (rec) begin
   we_0 <= addr[0]; //not sure why it isn't the inverse of addr[0] but that doesn't make the inverse on 'scope
   we_1 <= addr[0];
end
else begin
   we_0 <= 1;
   we_1 <= 1;
end
end

//VGA COLOR OUT

always @(posedge clk_in) begin
if (DEN) begin // I SOLDERED A WIRE HERE TO ACCESS DEN ON THE RPI !!
if (toggle==2'b00 || toggle==2'b01 ) begin
   r_out[3:2] <= data_out[1:0];
   r_out[1:0] <= data_out[1:0];
   g_out[3:2] <= data_out[3:2];
   g_out[1:0] <= data_out[3:2];
   b_out[3:2] <= data_out[5:4];
   b_out[1:0] <= data_out[5:4];

end else begin
   r_out[3:2]<= data_out[9:8];
   r_out[1:0]<= data_out[9:8];
   g_out[3:2]<= data_out[11:10];
   g_out[1:0]<= data_out[11:10];
   b_out[3:2]<= data_out[13:12];
   b_out[1:0]<= data_out[13:12];
end
end else begin
   r_out <= 4'b0000;
   g_out <= 4'b0000;
   b_out <= 4'b0000;
end
end

vga_sync vga_s(
.clk_in(clk_in),
.reset(reset),
.h_sync(h_sync),
.v_sync(v_sync),
.h_count(h_count),
.v_count(v_count),
.display_en(display_en) // '1' => pixel region
);

endmodule

From https://www.fpga4fun.com/VerilogTips.html:

• I need to initialize verilog counters !!
• Another way of selecting 4 bits in a vector : wire [3:0] thisis4also = myvalue[16+:4];
• It might be smarter to use a PLL than to take the external clock directly.
• I need to debounce all input buttons !

****

Check out shaders that take video as input :

https://www.shadertoy.com/view/ctsyzN

https://www.shadertoy.com/view/XtcSRs

****

Tried to make some vignettes of the new board to show the impedence matching :

I think I will order it in white with the meanders exposed like on the VGA spaghettini.

Color options (I’m leaning towards white or maybe green):

***************************

I am now thinking about how I will be able to share all that I am trying to learn about verilog and FPGAs in workshops. The bottleneck is programming the FPGA without special hardware.

OLIMEX has a link to a rasberry pi utility called flashrom that can program and read FLASH memory documented here : https://github.com/OLIMEX/iCE40HX1K-EVB/tree/master/programmer/olimexino-32u4%20firmware

These raspberry pi examples program the ice40 and looks simple :

• https://j-marjanovic.io/lattice-ice40-configuration-using-raspberry-pi.html
• https://github.com/plex1/raspice40

The steps have been automated here : https://notabug.org/sagaracharya/swarajya/src/master/hdl_to_hx8k/on_pi

Also for the rpi Pico : https://github.com/dan-rodrigues/pico-hx

I could knock off the 2232 FTDI and have made something like this: https://shop.trenz-electronic.de/en/TEM0009-02-FPGA-USB-programmer-JTAG-for-development-with-Microchip-FPGAs

Most interestingly, it seems like Arduino Uno could program an FPGA using a library like SPIMemory by Prajwal Bhattaram : https://github.com/Marzogh/SPIMemory/tree/v2.2.0

Finally, I could make a board like the gameduino that has an API for the Arduino to use to talk to the FPGA which handles fast screen drawing. This would mean everything could be done within the Arduino IDE.

EDIT* Come to think of it, even if the FTDI adds cost, it would make everything so much easier for a workshop – one piece of software and no extra hardware to program after for the participants. But when I plug it in it says USB device malfunctioned…(I also realized that I think I can forgo the RS232 connections between the FTDI and the FPGA and just connect it to the EEPROM and FLASH.)

EDIT* The OLIMEX code for Arduino is also not compiling and winIceProgDuino.exe (to program FPGA by sending serial commands to Arduino firmware I suppose) is not opening either.

EDIT*2 The Arduino sketch compiles but only for MEGA, Leonardo, and Micro so far (no UNO or NANO or MINI) but only after removing the iceprog.cpp file.

******************

Some thoughts on low-level versus high-level programming :

Something unsatisfying about making something from a pre-digested meta language (fast.ai for instance). Lost the feeling of ownership of the thing you’re making.

• https://projectf.io/posts/fpga-graphics/
• https://github.com/lawrie/hdmi_examples/tree/master

I have a month to work on a 45 minute lecture on my work at the Technische Universität München. I will also be doing a lecture at TU Darmstadt in November. I would like to use this opportunity to try to bring my video experiments into focus and incorporate it into my previous time-lapse projects.

This could take the form of a video series of me playing the prepared video buffer, possibly with explanations about what is causing what effect and demonstrative images / videos ? It could be contrasted with a “typical” workflow using the constraints of a software platform like photoshop? I could prepare this a similarly focused investigation of how the prepared piano altered sound, how Sonia Sheridan altered the photocopier, Paul Schafer made custom concrete music machines, etc.

EDIT* : I had a try !

• It’s kind of long and I also need to get a better top view.
• Adding text to describe what’s happening ?
• I also see that when I’m turning knobs the device is kind of hidden. I haven’t really designed the interface to be playable and to look good and be legible while being played.
• Looked into some other examples of video synth top down videos :

This is making me think more about the physical presence of my devices, and how I could incorporate more mechanical parts – instead of purely making electronics. I may have to play the game a bit more, make things that look like what they do and help people understand the associations I’m trying to make.

I could have micrometer heads for the potentiometers :

I could have fiber optic cables too :

I think if I every try to make a product though I would need to team up with someone who has skills I don’t.

***

Why make hardware ?

• it can be analog and digital
• it’s faster at doing things with video than software
• it can be custom
• it has a live-playable interface

***

What effects am I creating ? (check out Premiere to see what kinds of effects exist).

• Recording and playing things back at different speeds (video transposition), assigning to different color channels
• desynchronizing recordings with the screen sync so that they jump around
• recording videos side by side in memory so that they bleed over one another.
• Video collage and montage composer (video sampling, video looping), video plastifier, étude II, micro-montage, noise research, play, do and see, polyvideo layering, defamiliarizing of the image + reflecting the mediascape we inhabit, video as “palpable”, “nontheoretical”, and “experiential” (quotes from musique concrete wiki).
• The structure of the videos is based on the indexicality of the medium (the SRAM and how it stores). So the recording technique is also the synthesis technique.

Struggling to represent the painterliness of the raster videos without showing them as a video. It is completely different from my experiments with lines and triangles, and is less intuitive for me. An attempt at a kind of chronogram of a video :

It gives some idea of the range of images I guess?

Here are some notes I took about a year ago after visiting a painting expo that relate to my painterly video experiments :

• Layering
• Contour
• Surface
• Saturation
• Flow vs. Choppiness
• Roughness, relief 
• Edges versus centers
• Movement vs stasis 
• Enriching of detail
• Abstracting, cosmic making
• Fine lines versus coarse
• Exposure 
• Color fields
• Texture
• Deep friedness
• Films of cows, ocean. Stills of still life? Flowers, birds, drapes folding, mold, fruit, bones
• Color mixing vs melting vs meeting
• Paint viscosity (runny vs clotted)
• Direction of brush strokes 
• Contour
• Focus direction in canvas
• Translucent flesh, shine vs glow from interior, waxiness 
• Graininess 
• Composition, color pairings and form
• Foreground displaced to background vice versa 
• Meeting pattern planes 
• Lighting and shadow
• Illusion of depth
• Cloudiness 
• Turbulence

Check out this “glitch” video artist Jacques Perconte that Marc shared with me : https://www.youtube.com/watch?v=8_Xhu9Vx5XM

He works, since the 1990s, with compression and achieves a painterly, impressionistic effects and exposes them on immense projection surfaces.

Check out also Tauba Auerbach’s work :

Jack Whitten :

*************

Some quotes from Art21 series :

James Turrel – what you are perceiving is perception itself. We don’t receive the world around us we create it.

Jeff Wall – Art gives you an experience that alters something, it doesn’t tell you or convince you.

Jeff Wall – When I started photography there were potential energies in the medium that weren’t being realized.

Roland Barthes – The punctum points to those features of a photograph that seem to produce or convey a meaning without invoking any recognizable symbolic system.

Olafur Eliasson – Art provokes a negotiation : why I am seeing this the way that I am seeing it, what does looking mean? Instead of questioning the object you are questioning yourself. Art offers the opportunity for self-evaluation.

Tauba Auerbach – I want to learn things all the time, I want to understand the patterns behind things. I experience science through craft. With craft I try to cultivate sensitivity in a practiced, purposeful way. If you work with marbling you know just as much about viscosity and flow than a scientist, through your fingertips in a different way.

Tauba Auerbach – Ideally I want to make an image that has a tiny effect on all the future images that you see.

Tauba Auerbach – The pursuit of the sweet spot, cultivate the place of boundaries, limits of fraying, not hard edges.

Cindy Sherman – I don’t know what I’m looking for until I see it.

Richard Serra – Artists invent strategies, tools, techniques, that allow themselves to see in a way they haven’t seen before to extend their vision beyond the standardized classic reflex actions. These help us to see inside what we’re doing so we don’t get into a lock step notion of how to do what you do.

Louise Despont – If you’re always making work for someone, and not for yourself, maybe you don’t let yourself make the mistakes that are necessary.

Louise Despont – Each drawing is a series of tiny discoveries, it reveals/unfolds the drawing from total control. I own at most 1/4 of the drawing. The rest is something else, this is what’s exciting.

Louise Despont – It’s best explained in the drawings, words are clumsy to describe something like the concrete feeling of spirituality.

Liz Magor – My Studio is a space to reconcile dissonance, no one knows I’m here. When I’m not in my studio I want to be in my studio working. My tools are rudimentary. I’m here for pleasure but it’s not fun. Everyone should have a studio for mental health. I can filter out the noise and see the ever present under the radar stuff.

Liz Magor – I’m not an animist but objects have stuff in them that comes out. I try to resurrect these objects from the netherworld.

Liz Magor – The slowness of the material process matches the slowness of my thinking process.

Liz Magor – I’m creating an experience for looking.

Liz Magor – I give myself my own program, I give myself my own assignments. And art is the choices I make.

Liz Magor – Maintaining the conditions for this production, which is not very logical, uncalled for. No one is asking me to do this, I’m barely asking me to do this. To do this I have to overlook my making with the journey of the things into the world.

Liz Magor – After the casting I unwrap it like a little gift, there are surprises.

Elliott Hundley – This photoshoot is so elaborate but not because I want a certain effect, because I want to not control the effects, and have a layer of unexpected results. In relinquishing control, the piece gives me something back I didn’t expect.

Jack Whitten – I’m not a narrative painter.

Jack Whitten – I built a device to move large amounts of acrylic paint in one gesture.

Katherina Gross – Painting is not linear. The synchronicity in painting is compelling for your thought process. I’m trying to grasp some of those fast thoughts that are moving through my brain.

*************

Reading about the history of video synthesis.

From https://museumzero.blogspot.com/2013/12/its-all-baseball-nam-june-paik-starts.html)

Nam June Paik sees Taoist energy in working with the flow of TV video :

“To receive simultaneously the parallel flows of many independent movements is, as Paik pointed out at the time, a classical Taoist way of meditating: by becoming aware of everything going on in the present, you discover eternity right now.” 

“I love Chinese history, surprise, nonlinearity.  You know what judo means?  A way to be soft.  You let other guy do all the work.  I think in some Oriental way.  In TV I try not to be boss, to stay as small as possible.  So that seems to work. “ 

“So then when I started TV, the best decision I made in life is not really to go into TV, but to do work inside TV.”

“Imagine everything that exists is flowing, like the tao, in a perpetual motion, with endless waves, like the ocean.  We come from it; we go back to it.  Whatever surges forward falls back, so Lao-tse, who wrote the Tao Te Ching (On the Nature of the Way), urges us not to try too hard.  Relax; be like a baby; follow whatever path presents itself.  That is the way. ”

Not striving to fit yourself to some preconceived ideal, like a Buddhist or a Confucian; simply being, following breath wherever it blows.  In this sense, the television signal is like the tao; endlessly variable, continually reversing itself, dying, being reborn, it is never idle, yet it is so vast and perpetual that it often seems calm as the sea.

Beginning with whatever live programs came along, distorting them, then recombining his distortions like waves on the ocean surface, Paik created an indeterminate and endless show for the Galerie Parnass, in Wuppertal, Germany, in 1963.  

From Scanimate: The Origins of Computer Motion Graphics :

• This is about the history of television, these were the first ways to put text and make graphics on screen (Media Archaeology!). Nowadays visuals are gratuitous. What did we lose in the transition to digital ? The imperfections, the proximity to the functioning.
• Had a role in music videos, and news segments, so was part of culture.
• “Blooming” is the term for the glowing edges in CRT Scanimate.
• It’s real life artefacts. It’s like exploding scale models instead of GCI.
• They made cookbooks with the recipes of different effects that created while working with clients.

From https://wearethemutants.com/2018/01/09/a-sloppy-machine-like-me-the-history-of-video-synthesizers/

Like its close temporal and conceptual counterpart, the audio synthesizer, the video synthesizer was created iteratively by academics, artists, and tinkerers, then eagerly snatched up by the world’s biggest media producers once prototypes had proved their power and versatility.

• Started with experimental musicians like John Cage and la musique concrète.
• Early pirate TV station in NYC.
• Amiga supplants the Scanimate and analog synths.
• The 1967 Portapak release and it’s importance for activism and experimental art.
• Video comes from the root video of Latin video (“I see”).
• There is a relationship between images and waves  :

CC BY-SA 3.0, https://commons.wikimedia.org/w/index.php?curid=641492

This is so hard for me to understand but this somehow relates to chirping also :

By Drummyfish – Own work, CC0, https://commons.wikimedia.org/w/index.php?curid=77608151

More cool matrix math image modifications here : https://en.wikipedia.org/wiki/Digital_image_processing

Also this website which describes it all visually ! https://setosa.io/ev/image-kernels/

From Video Art : An Anthology :

• • The synthesizer let’s you see things that exist only in the mind’s eye.
  • visual ingredients
  • video synthesizers churn out…images based on their own electronic structure.
  • We make the image with our eyes and brain. It’s psycho-visual
  • video as concretized imagination.
  • video is surreal, the images are ephemeral products of micro electronic pulses.
  • “electronic imagery”
  • video is a medium which works with time

The Vasulkas

*************

Here is an attempt to describe what could be a model of a potential “practice” :

*EDIT* This should include me blogging ! Maybe add a RESEARCH and/or DOCUMENTATION phase ?

*******

Check out this pyramid of types of work :

I feel like my project is about analysing (and curating), I’m not sure if I take a real position.

*******

Check out this amazing NIME article called The Concentric Sampler: A musical instrument from a repurposed floppy disk drive by Timothy Tate about “the redundancy and physicality of magnetic recording media” which utilizes “time-based granular synthesis” and lo-fi:

https://nime.pubpub.org/pub/uh76shf0/release/1

Some quotes :

• Physical media offer an opportunity to “foreground the physical medium as a tool for musical expression.”
• “The deterioration of old magnetic tape as it is looped, defining a … musical structure.” The “failure of the medium is in focus, rather than the mechanism.”
• “as soon as something’s on tape, it becomes a substance which is malleable and mutable and cuttable and reversible in ways that discs aren’t.”
• “This study emphasises working within a medium’s limitation, rather than prescribing a compositional framework or sonic agenda upon it”
• Motivation to “foreground musical and technical possibilities…and generative sonic potentials…and novel, unique expressive and
• compositional possibilities”…to be “discovered…explored”
• The device is a “performable instrument and a generative sonic tool”
• “Rather than focusing on the authenticity of the sound reproduction, the Concentric Sampler draws focus to the byproducts and the resultant indexicality and generative sonic possibilities of the floppy disk as a medium.”
• “the term ‘musical expression’ here places value on the ability to shape and define a musical grammar from the indexicality of the …medium and mechanism.”
• “subverting traditional modes of … expression“
• “Each section is accompanied by a demonstrative video” !!!
• The live playable instrument can “achieve the dissociation of pitch and time“
• “imperfections in … reproduction”

• “possibilities within a framework of … making”

Now following up on some of the references from this article:

• You can think of an instrument as a framework that has a predisposed range (affordances). Our tools provide a certain range of suggested usages. Some things are easier and some things harder to do with an instrument, this is the instrument’s spectrum. If you stay within those ranges, you accept the silent grain of the instrument. If you make an unusual tool then, do you risk finding yourself in an unusual affordance ? (J. Mooney) Could it be possible to make videos subtractively, instead of additively ?
• From New Media Reader : The different between representation and simulation. P.18″Digital media process the physical properties of the input data, light and sound waves, are not converted into another object but into numbers; that is, into abstract symlbols rather than analogous objects and physical surfaces. Hence, media processes are brought into the symbolic realm of math rather than physics or chemistry. Once coded numerically, the input data in a digital media production can immediately be subjected to the math processes of addition, subtraction, multiplication and division…” AND compressed AND manipulated more easily than analogue forms because they are more mutable than objects. Also easy access and quick movement of the data of an enormous mass of data. This causes the materiality of the world around us to become unsteady…The televisual
• Because everything else is also digitized, there is a “convergence of previously discreet media forms, now a new fluid area of media decentralized production and consumption. Remediation, Multilinearity.
• Hand-made videos. Exploring the boundary between hand tools and large-scale machines which is a distinction Marx makes P.91.

Check out these Bauhaus era artist’s work with the audio band in video :

Paul Schaeffer (coiner of the “club d’essai“) designed specific tools like the morphophone and phonogène for modifying audio for musique concrete :

*******

Watching ENSCI diploma presentations I’ve thought about how nice the sequence is : first you write something that explores a topic and cites thinkers on the subject, and then you work on a design project that relates to this somehow. Also looking back at some videos, there is already a lot of content I have produced that I could try to learn from ! Like that Amsterdam-based artist told me, I could also focus on using my tools.

I am also doing a synth workshop in late September at Villette Makerz but I’m not sure if I can connect to that or not here. *EDIT* an FPGA board that generates patterns based on audio input is a GO !*

I also want to make a next FPGA board which will be a software reconfigurable device so that I can move to verilog for the summer instead of making a new board for every experiment. Not sure if this could also take the form of a simple video synth for Villette Makerz or at least a simplified version perhaps.

*******

Some quick looking in to GPUs :

GPUs are all about direct memory access (DMA) not mediated through the CPU. A thought about the FPGA board – perhaps I should first have Arduino mess with the clock while playing back / recording something on the 16MB board (but I’m limited to the number of pins for address and I/O – it would essentially be a counter that could change in frequency on the fly)? Having memory connected to the screen (a screen buffer) and modifying it is the fundamental computer display setup. From 1951 a memory pattern on CRT :

It would be cool to experiment with sprites and copying parts of memory from one bank to another too like a blitter https://en.wikipedia.org/wiki/Blitter .

It looks like what makes shaders cool is that they are programmable and have their own code languages now. Before shaders there were hardware rendering pipelines called fixed-function. Different units would be responsible for specific functions. It seems like these units would take in vertex data then output pixel colors.

I looked in to how to do matrix multiplication in hardware. It actually seems to be more natural as an analog circuit with resistor arrays. It can also be done by multiplying two 2-bit binary numbers using this kind of logic setup :

**********

I am becoming more and more curious about the difference from having a screen buffer that is written to during the blanking period and having a massive bank of memory that can be recorded to like in the 128Kbit. Check out these articles about how writing and reading to video memory is dealt with in different systems :

https://en.wikipedia.org/wiki/Tiled_rendering

https://en.wikipedia.org/wiki/Multiple_buffering

https://en.wikipedia.org/wiki/Vertical_blank_interrupt ,quoted from : 

“During the vertical blanking interval, the driver orders the video card to either rapidly copy the off-screen graphics area into the active display area (double buffering), or treat both memory areas as displayable, and simply switch back and forth between them (page flipping). [The two buffers are called the front and the back buffer] Some graphics systems let the software perform its memory accesses so that they stay at the same time point relative to the display hardware’s refresh cycle, known as raster interrupt or racing the beam.” [i.e. you can also draw things during the horizontal blanking interval]

**********

The Real-Time Corrupter is fascinating https://redscientist.com/rtc . The kinds of memory modifications it allows for are fascinating and far more dynamic than static, text-based find-and-replace experiments I’ve done in workshops. Looking at this video I learned some cool stuff (https://www.youtube.com/watch?v=n9HS6zftuSk&list=PLItZ3jvJKD7rnoxmqJJ0B5E1B9_WW9L5E&index=2). For instance, copying values from one address (in video RAM, scrolling backdrops memory space a.k.a. “nametables”, NES RAM, ROM etc.) and then reapplying them to another address every frame (called piping) or just one time, the ability to isolate specific effects with the sanitize function. It can generate noise between certain values, or shift values up or down on (called tilting), listen to a value and then reapply it after a fixed number of frames, freezing the current value somewhere for future frames, replacing values intelligently with values in certain sets (for 3D glitching). It’s like performing brain surgery while the patient is fully conscious and telling a story. All of these memory transformations could be applied with the FPGA board !

**********

In a similar spirit, this game called Code War involves creating a program that competes with others to write to all of the memory space. There are competing strategies (quoted from https://corewar-docs.readthedocs.io/en/latest/corewar/strategies/) for warriors :

Rock - a warrior which rapidly bombs the core with dat instructions
Paper - a warrior which replicates, creating multiple, parallel copies
Scissors - a warrior which scans the core looking for other warriors

The battle is visualized in a memory grid (https://corewar-docs.readthedocs.io/en/latest/corewar/visualisation/)

You can simulate and battle warrior code here : https://crypto.stanford.edu/~blynn/play/redcode.html

**********

Visualizing memory access in time. From https://bling.kapsi.fi/blog/x86-memory-access-visualization.html:

*********

Some thoughts on HCI from people at work :

it’s research if it follows scientific method and has possible applications.

Find your peers, try to publish in their journals.

The idea of publishing is to get feedback from your peers.

If you make a pedagogical tool, then you could test how effective it is at helping people learn.

Based on this conversation, I thought about how I don’t necessarily want to promote engineering education and that I always want to be on the design/art side of things. I also have learned that I find doing something I already know how to do less exciting, and so making simple kits or small series of artworks that are guaranteed to work for days on end, is not always super rewarding for me intellectually. This leads me to the current conclusion : I want to teach and then do a kind of artistic research on the side. I should then keep building my teaching career and try to get expos of my work. I am still trying to figure out how exactly my artistic research should be communicated (through articles in design magazines, through conferences with expos connected to them?).

**********

I am preparing a solar workshop at Villette Makerz based on the simple solar engine with optimized SMD components. The idea is an art bot that will draw, paint, in the sun. I am working on testing the various combinations of solar panels, capacitors and voltage supervisors.

We are also making a version 2 of the video synth modules which are all Eurorack compatible in terms of dimensions, use 3.5mm audio jacks, the eurorack power supply. The idea is that the modules be both manual and automatable for the purpose of demos and to be didactic for students learning about analog electronics.

Marc is doing a great job reimagining this project – he is good at compromising and imposing the vision of the final thing on each step of the construction. I am, in contrast, driven astray I think by my fascination by what “the machine itself wants to express”…

********

Finally getting around to testing the Arduino-controllable analog switch to activate record or READ mode on the SRAM 16MB board. The idea is to test taking a recorded video and then doing some bit manipulations with it and saving it back to the memory. Predictably though, I’m having issues just writing anything to the thing…

I/O pins on Arduino 0-7
CLK on Arduino 12
REC on Arduino 13 connected to analog switch connecting the WR pin on SRAM to either VCC or !CLK

unsigned long memory; //total number of 8bit words on the 16Mb SRAM = 2048000

const byte IO_0 = 7; 
const byte IO_1 = 6; 
const byte IO_2 = 5; 
const byte IO_3 = 4; 
const byte IO_4 = 3; 
const byte IO_5 = 2; 
const byte IO_6 = 1; 
const byte IO_7 = 0; 

void setup() {
//Serial.begin(115200);
pinMode(13, OUTPUT);
pinMode(12, OUTPUT);

pinMode(IO_0, OUTPUT);
pinMode(IO_1, OUTPUT);
pinMode(IO_2, OUTPUT);
pinMode(IO_3, OUTPUT);
pinMode(IO_4, OUTPUT);
pinMode(IO_5, OUTPUT);
pinMode(IO_6, OUTPUT);
pinMode(IO_7, OUTPUT);

//WRITE
while(memory<= 2048000){
memory++;

// if (memory%10000==0){
// Serial.println(memory);
// }

if (memory%5==0){
PORTD = B11110000; // the IO pins. simple pattern test.

}
else{
PORTD = B00001111;// the IO pins. simple pattern test.
}
//WRITE MODE
PORTB = B11101111; // PIN 12 ARDUINO CLK goes LOW/HIGH
PORTB = B11111111; // PIN 13 ARDUINO WR STAYS HIGH

}
// Serial.println("finished writing");
}

void loop() {
pinMode(IO_0, INPUT);
pinMode(IO_1, INPUT);
pinMode(IO_2, INPUT);
pinMode(IO_3, INPUT);
pinMode(IO_4, INPUT);
pinMode(IO_5, INPUT);
pinMode(IO_6, INPUT);
pinMode(IO_7, INPUT);

digitalWrite(IO_0, LOW);
digitalWrite(IO_1, LOW);
digitalWrite(IO_2, LOW);
digitalWrite(IO_3, LOW);
digitalWrite(IO_4, LOW);
digitalWrite(IO_5, LOW);
digitalWrite(IO_6, LOW);
digitalWrite(IO_7, LOW);

//PIN 13 REC IN LOW READ MODE
PORTB = B11011111; // PIN 12 ARDUINO CLK goes LOW/HIGH
PORTB = B11001111; // PIN 12 ARDUINO CLK goes LOW/HIGH
}

unsigned long memory; //total number of 8bit words = 2048000
byte cell; // store the word at this address

void setup() {

//PD0 - PD7 are IO
pinMode(13, OUTPUT); // REC - PB5
pinMode(12, OUTPUT);// CLK - PB4

 while(memory<= 2048000){
    memory++;
//READ
        DDRD = B00000000; // all IOs in INPUT
        PORTD = B00000000; // no pull-ups

        PORTB = B11011111; // WR stays LOW + CLK HIGH
        delayMicroseconds(10);
        cell = PIND; // read the cell at this memory address and store it in the variable cell
        delayMicroseconds(10);
        PORTB = B11001111; // WR stays LOW + CLK LOW
        delayMicroseconds(10);

//WRITE
       
        DDRD = B11111111; // all IOs in OUTPUT

        PORTD = ~cell; // write  a transformed cell back to memory
        PORTB = B11111111; // WR stays HIGH + CLK HIGH
        delayMicroseconds(10);
        PORTB = B11101111; // WR stays HIGH + CLK goes LOW
        delayMicroseconds(10);
  }
}


void loop() {
//READ MODE TO SEE WHAT WE HAVE IN MEMORY
        PORTB = B11011111; // WR stays LOW + CLK HIGH
        delay(500);
        PORTB = B11001111; //  WR stays LOW +  CLK LOW
        delay(500);
}
Not working either...

Heading towards a more reliable, deployable and software-leaning approach (but not so much about automated choreography as with previous atmega boards as augmented live playable machine for manual performances) to working with video now.

I am also trying to be a bit more strategic and attempt to think ahead a little bit beyond the one board one experiment situation. It takes a long time to trouble shoot a single board and learn all the lessons from it, I have to give each board the time it deserves and I need to be perhaps less productive and more thorough.

I am also coming to the awareness of what is my scope with this next board :

• I won’t be doing challenging engineering things (like implementing different ways of programming the same FPGA, interfacing with differential pair protocols like HDMI) that have no impact on the images and take loads of time to do.
• These are boards for experimenting and live playing, so they also need to have controls on the board.
• I also need to think about safety, avoiding the possibility of easily making short circuits and damaging the board.
• I’d also like to move back to color, and away from the intense limits of exclusively 1bit resolution.
• I want to keep removing superfluous cables and adapters too, this one will have only a VGA out.

I made a map of my prototypes so far for this project :

It’s been around two years I’ve been working on this !

After talking with Zach at work, his idea was to show not just the screen but also me turning knobs etc. Here’s what this could look like :

Or,

…or,

It would be nice to have a computer interfaced oscilloscope to record the signals.

*****

The most plug and play option would appear to already exist : a tiny raspberry pi zero can already run Processing scripts and control small screens https://learn.adafruit.com/processing-on-the-raspberry-pi-and-pitft/processing !

Here’s a good intro to making simple patterns with processing : https://processing.org/examples/

We would be more in the zone of software video synth : https://learn.adafruit.com/feather-rp2040-dvi-video-synth

Also seem to be companies making just this kind of thing : https://store.excamera.com/

Arduino talks to the FPGA by SPI as if it were a RAM space. https://excamera.com/files/gameduino/synth/doc/gen/poster.pdf

Design / Engineer friend Paolo Salvagione pointed me to Configurable mixed-signal ICs. It appears to be like an FPGA but for mixed analog and digital circuitry and is configured in design software.

There is also the world of ASICs and the google open-source silicon project https://developers.google.com/silicon

*************

My project was originally about slowing down computer processes and representing them in space. Now I just seem to order things on Amazon and design increasing numbers of PCBs. It seems that I have so little time to do the art in the end because of how much investment the technical stuff requires. How could I get back to my original project here ?

My project also had a collection of related techniques :

• Try to free machines from their corseted, factory settings and reveal their full range of expression that would otherwise just exist in a parallel unseen dimension
• Try to show our files from the perspective of / through the eyes of the machines that are processing them.
• Curate series of abstract formal compositions which emerge from figurative, architecturally-themed or culturally iconic ones.
• Try to describe the behaviour / idiosyncracies of algorithms and make them tangible
• Isolate specific moments of machine-to-machine interface in a larger system
• Get one’s hands inside the black box, and make prepared machines which expose their parameters
• Try to rebuild electronic systems based on help from the DIY internet and then hope to stumble on something unintentional
• All the while emphasize the materiality of technology
• Trying to go super low-level and avoiding abstract computer “visualizations”
• Exploring the link between visual chaos and harmony, that sweet spot of medium entropy.
• Riffing off of the music synthesizer movement of knobs and playful electronics interfaces and its anti-theory vibe
• Exploring the surreal, bizarre space of the computational unconscious
• Do “artistic research” projects that are educational, at least for me
• play with form versus content

I wonder if the pixel based screen is not really appropriate for my methodology. It’s the opposite of over-looked and black boxed. It’s an obsession for an entire culture. It also does a pretty good job of “representing” what happens inside the computer already. It doesn’t really need my help !

********

I also need to do a debrief on this leg of the video synth project. What have I learned ?

Technical stuff :

• • • How to make and debug PCBs
    • To work with video + SRAM with counters as well as some op amp circuits. The difference between digital and analog in the video context.
    • To work with the VGA protocols, about resolution and brightness of the image.
    • I learned about oscillation, the difference between KHz and MHz in the context of video and what sampling is.

Stuff about media representation

• • • some aspects of the nature of visual memory, how some of our sensory apparatus work at different speeds
    • the curious experience of “searching” for an image (like when messing with ADC knobs and CLK speeds).
    • what is required to identify / recognize and image or scene, how much resolution and shape
    • Deconstructing the illusion of television by interacting with its materiality and mutability
    • Repeating historical art explorations with television (see Sans Soleil – Chris Marker)
    • synchronizing the data with the frame of the image is a key part of the illusion of video. If you mess with this suddenly the video frame becomes a malleable object. If it is desynchronized, the image is out of frame and will jump around with the SRAM recording. If you change the speed of recording or of playback you can zoom.
    • Layering of different images in a palimpsest can create textures from them.
    • I’ve made some nice abstract pattern discoveries through knob twisting.
    • Exploring the gap between legible figurative image and abstract patterns, contours, fields,
    • the texture and grain of data at various scales
    • the connection between video and abstract field painting

What does it mean to be trying to make super simple hardware video filter in the age of AI generated video and images ? How is this activity relevant ? I feel like I’m looking for low hanging fruit here but I’m not sure there is any left. Also, the time it takes to make a single experiment in hardware is astronomical compared to the software option…

I think the project started off about the screen itself, how to send signals and display them. At some point it became clear that the screen just displays data stored in memory.

In this spirit, I could try to represent memory access patterns : https://en.wikipedia.org/wiki/Memory_access_pattern Or the patterns that memory is refreshed in : https://en.wikipedia.org/wiki/Memory_refresh

http://www.overbyte.com.au/misc/Lesson3/CacheFun.html

I could also sample images and then modify them algorithmically? But it kind of ends up looking like simple Photoshop filters. It would have to be modified in some way based on the way the image is stored in the memory ?

Check out this image stored in DDR ram decaying over time from J. Alex Halderman’s paper : https://jhalderm.com/pub/papers/coldboot-sec08.pdf

Also it seems like different DDR has different decay rates (from A Trustworthy Key Generation Prototype Based on DDR3 PUF for Wireless Sensor Networks https://www.researchgate.net/figure/DRAM-cells-decay-feature-with-power-switch-interval-time-of-120-s-a-DDR3-device-1-b_fig3_263586301):

For comparison, check out the same Mona Lisa image sent through the air and damaged by the earth’s atmosphere :

********

I’ve never thought of this before but I guess I could generate a simple arduino code, and then take the .hex file and glitch it with any of the glitching techniques I’ve been using and see what it puts on screen.

I could also test overclocking / overheating the atmel and seeing how they collapse !!

********

I should also finish the boards I’ve already designed and had made, they offer learning opportunities and possible discoveries ! The bucket brigade, the digitally-controlled pots (meh), and the band splitter (*EDIT* completed !) are the three that are left from that series. Also the Palimpsest.OS 2 board when controlled by microchip – especially if I can get the sync working ! Of course I have the new 128Kbit memory board (*EDIT* all done !) once I get the parts too and then a final (?) FPGA v2 board.

********

I am still interested in exploring FPGAs and getting my hands in the tech to possibly stumble on cool stuff though so here is a second attempt at a video FPGA board based on the iCE40HX1K-TQ144 to output HDMI, DVI, VGA, and composite video.

For generating verilog, there is migen for python 3 (https://github.com/m-labs/migen). I’m going to try a super simple thing in Verilog first to get a feeling for it. 

I am learning verilog here : https://hdlbits.01xz.net/wiki/Main_Page

It looks like generating HDMI is doable even though there is a difference between LVDS and TMDS (involving possibly 100nF series capacitors ?) :

Here is the official guide : https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/UZ/FPGA-TN-02213-1-7-Using-Differential-IO-LVDS-Sub-LVDS-iCE40-LP-HX.ashx?document_id=47960

https://www.fpga4fun.com/HDMI.html

blackmesalabs.wordpress.com/2017/12/15/bml-hdmi-video-for-fpgas-over-pmod/

https://github.com/hdl-util/hdmi/

Different chips being used like the PTN3360D HDMI / DVI Level Shifter (IN STOCK!), a TFP410PAP TFP410 TI PanelBus™ Digital Transmitter (NO STOCK!),

According to the datasheet, “The LVDS25E/subLVDSE differential output buffers are available on all banks but the LVDS/subLVDS input buffers are only available on Bank 3 ofiCE40 LP/HXdevices.” ***Those are INPUTS but there are no special OUTPUT pins.***

I have replaced the LDO with was giving me trouble previously and am making this version USB programmable so it could be a useful for others as a cool video kit.

*****

Revisiting FPGA programming, here is where I got to last time :

Here is my process for the FPGA programming so far :

1. I signed up for an account at www.latticesemi.com.
2. I got a licence for iCEcube2, put it somewhere easy to find and took note of the directory, and downloaded iCEcube2 and the Lattice Diamond software from here : https://www.latticesemi.com/en/Products/DesignSoftwareAndIP
3. I plugged in the iCEstick and it blinked in a circular pattern. I also checked that it had a port under Device Manager (it had 2!). 
4. I went into iCEcube2 then to Help > Tutorial to open a pdf called “Implementing the Design” and followed the following steps :
   1. Start new project (iCE40, HX1K, ?TQ144?)
   2. Add Design file iCElab.v and Constraint file iCElab.sdc and checked the Device Info.
   3. Run Synplify Pro Synthesis
   4. Select Implementation
   5. Add constraint file iCElab.pcf under Import P&R Input Files.
   6. Run Placer
   7. Check the Floorplan, package view, timing analysis, power estimation
   8. Generate the bitmap (.bit and .hex files) which is saved wherever the project was saved. (For instance C:\Users\Jonah\Desktop\FPGA LATTICE DEMO PROJECTS\quick_start\quick_start\quick_start_Implmnt\sbt\outputs\bitmap).
   9. Here is what everything should look like once finished :
   10. 
5. I then transitioned to Youtube for a detailed explaination of using Diamond Programmer with the iCEstick here : https://www.youtube.com/watch?v=Df9k1T0bHmA&ab_channel=Dom
   1. Launch Diamond Programmer and take the default options (or click scan and take those). Important to note that you must launch Lattice Diamond Programmer directly, not through Lattice Diamond, in order to find the iCE40HX1K chip.
   2. It will mistake the board for a JTAG interface and give the following errors : “Failed to scan board”, “Scan Failed – Creating Blank Programmer Project.”
   3. Now change the Device Family to iCE40, the device to iCE40HX1K, and under Program enter the following information :
      1. Change Access mode to SPI Flash Programming and now some other options appear. Select > Vendor: Micron, Device: N25Q032, Package:  8-pin VDFPN8
      2. Now load the bitmap (.bin) file and check that it has a non-zero datasize :
      3. 
      4. Click OK and then click the green traffic light on the next to top row of icons. You should then see a completion message and have the program on your board :
      5. 
      6. Presto !

Just for info :

For the actual pinout of the ice40 (which you can change in Pin Constraints Editor):

***

And here is my attempt programming my own board with the Lattice Programmer.

I followed the same steps as above but instead selected the HW-USBN-2B (FTDI) programmer. Important to note that you must launch Lattice Diamond Programmer directly, not through Lattice Diamond, in order to find the iCE40HX1K chip. Also note that you need Lattice iCEcube2™ Software, not just Diamond for some reason.

Here are the color connections needed from the Lattice Programming Cables User Guide :

The USB power and Board power lights should be on on the programmer and the Prog blue LED should flash a few times before the Done blue LED will flash and Lattice Programmer will display Operation: successful.

I am taking the example LED rotation verilog .v code :

module LED_Rotation(

    input  clk,
    output LED1,
    output LED2,
    output LED3,
    output LED4,
    output LED5

    );

               reg[15:0] div_cntr1;
               reg[6:0] div_cntr2;
               reg[1:0] dec_cntr;
               reg half_sec_pulse;                         

               always@(posedge clk)
                              begin
                              div_cntr1 <= div_cntr1 + 1;
                              if (div_cntr1 == 0)
                                            if (div_cntr2 == 91)

                                                           begin
                                                           div_cntr2 <= 0;
                                                           half_sec_pulse <= 1; 
                                                           end
                                            else
                                                           div_cntr2 <= div_cntr2 + 1;
                              else
                                            half_sec_pulse <= 0;                            

                              if (half_sec_pulse == 1) 
                                            dec_cntr <= dec_cntr + 1;                                          
                              end                                                            
               assign LED1 = (dec_cntr == 0) ;
               assign LED2 = (dec_cntr == 1) ;
               assign LED3 = (dec_cntr == 2) ;
               assign LED4 = (dec_cntr == 3) ;
               assign LED5 = 1'b1;
                                                     
endmodule

module vga_sync_test(
    input wire clk_in,
    input wire reset,
    output reg r0,
    output reg r1,
    output reg r2,
    output reg b0,
    output reg b1,
    output reg b2,
    output reg g0,
    output reg g1,
    output reg g2,
    output wire h_sync,
    output wire v_sync,
    output wire led,
    output wire locked_led
  );

wire clk_sys;
wire display_en;
//reg [9:0] h_count;
wire [9:0] h_count;
//reg [9:0] v_count;
wire [9:0] v_count;
assign  led = clk_sys;

localparam  h_pixel_max = 640;
localparam  v_pixel_max = 480;
localparam  h_pixel_half = 320;
localparam  v_pixel_half = 240;

//Check if we can create RGB colors
always @(posedge clk_sys) begin
  if (display_en) begin
    if (h_count < h_pixel_half
        && v_count < v_pixel_half) begin
      //Assign here your test color
      r0 <= 1'b0;
      r1 <= 1'b0;
      r2 <= 1'b0;
      g0 <= 1'b0;
      g1 <= 1'b0;
      g2 <= 1'b0;
      b0 <= 1'b1;
      b1 <= 1'b1;
      b2 <= 1'b1;
    end else if (h_count > h_pixel_half
            && v_count < v_pixel_half) begin
      //Assign here your test color
      r0 <= 1'b0;
      r1 <= 1'b0;
      r2 <= 1'b0;
      g0 <= 1'b1;
      g1 <= 1'b1;
      g2 <= 1'b1;
      b0 <= 1'b0;
      b1 <= 1'b0;
      b2 <= 1'b0;
     end else if (h_count < h_pixel_half
            && v_count > v_pixel_half) begin
      //Assign here your test color
      r0 <= 1'b1;
      r1 <= 1'b1;
      r2 <= 1'b1;
      g0 <= 1'b0;
      g1 <= 1'b0;
      g2 <= 1'b0;
      b0 <= 1'b0;
      b1 <= 1'b0;
      b2 <= 1'b0;
    end else begin
      //Assign here your test color
      r0 <= 1'b1;
      r1 <= 1'b1;
      r2 <= 1'b1;
      g0 <= 1'b1;
      g1 <= 1'b1;
      g2 <= 1'b1;
      b0 <= 1'b1;
      b1 <= 1'b1;
      b2 <= 1'b1;
      end
  end else begin
    r0 <= 1'b0;
    r1 <= 1'b0;
    r2 <= 1'b0;
    g0 <= 1'b0;
    g1 <= 1'b0;
    g2 <= 1'b0;
    b0 <= 1'b0;
    b1 <= 1'b0;
    b2 <= 1'b0;
  end
end

vga_sync vga_s(
      .clk_in(clk_in),         //12MHz clock input
      .reset(reset),           // RST assigned to SW1
      .h_sync(h_sync),
      .v_sync(v_sync),
      .clk_sys(clk_sys),       //25.125 MHz clock generated by PLL
      .h_count(h_count),
      .v_count(v_count),
      .display_en(display_en), // '1' => pixel region
      .locked(locked_led)      // PLL signal, '1' => OK
      );

endmodule

set_io b0 76
set_io clk_in 21
set_io led 99
set_io r0 81
set_io b1 75
set_io g2 91
set_io r1 80
set_io v_sync 87
set_io b2 74
set_io g1 95
set_io locked_led 142
set_io r2 79
set_io reset 2
set_io g0 96
set_io h_sync 88

$display("0.5 seconds");

run -all

module dut ( input clk ); 

`timescale 1ps / 1ps
module top_module ( output reg clk );

      dut instance2 (.clk(clk));

           initial begin
           clk = 1'b0;
           forever #5 clk = ~clk;
     end
endmodule

module top_module(
input clk,
input load,
input [511:0] data,
output reg [511:0] q);

always @(posedge clk) begin
       if (load)
           q <= data; // Load the DFFs with a value.
       else begin
          // At each clock, the DFF storing each bit position becomes the XOR of its left neighbour
          // and its right neighbour. Since the operation is the same for every
          // bit position, it can be written as a single operation on vectors.
          // The shifts are accomplished using part select and concatenation operators.

         // left                     right
         // neighbour              neighbour
           q <= q[511:1] ^ {q[510:0], 1'b0} ;
        end
    end
endmodule

`include "rule90.v"
`timescale 1ps / 1ps


module rule90_tb();
reg clk;
reg load;
reg [511:0] data;
wire [511:0] q;

rule90 DUT (
.clk(clk),
.load(load),
.data(data),
.q(q)
);

initial begin
#10
clk = 1'b1;
#10;
clk = 1'b0;
#10;
load = 1'b1;
data = 1'b1;
clk = 1'b1;
#10;
clk = 1'b0;
#10;
load = 1'b0;

end

always #10 clk = ~clk;
endmodule

Making things easier, simpler, more plug and play.

****

Workshop
Organize parts 

Palimpsest.OS
Get all channels working 
Get raspberry pi VGA out working 
Test with raspberry pi VGA put 
Fix VGA input/output (I know what the problem is at least :)!
SPI SRAM 
Get recording as fast as possible 
Try with 4MB FRAM ?
New board with several + raspberry pi + snake-like channel overwriting?

FPGA
Try simple VGA with LatticIce40
Solder FPGA board 

I’ve got a Raspberry Pi Zero outputting VGA nicely. On startup it launches VLC in fullscreen and plays a playlist of iconic film excerpts. I activated hotplugging so it keeps looping even if the adapter is unplugged for long periods of time.

I used Win32DiskImager and downloaded the ISO Image Raspberry Pi OS with desktop (around 1GB) from the officiql website (https://www.raspberrypi.com/software/operating-systems/) and put it onto an 8GB SD Card.

In terms of connectors I needed a SD Micro > SD card adapter, HDMI mini > HDMI, an HDMI > VGA, a USB A > USB Micro for power, and a USB Micro to USB A female in order to plug in a mouse / keyboard.

I followed these three tutorials for setting up VLC autoplay and turning off annoying VLC text:

https://forums.raspberrypi.com/viewtopic.php?t=17051

Raspberry Pi: Run VLC on startup and play slideshow videos/pictures from folder

https://www.shellhacks.com/raspberry-pi-force-hdmi-hotplug/

Now adding a power off button (not good to pull the plug while running)

https://howchoo.com/g/mwnlytk3zmm/how-to-add-a-power-button-to-your-raspberry-pi

**EDIT The rasbpi turns off when I unplug HDMI or plug into the palimpsestOS. Is it because RGB are mixed with only 100ohm resistors ? Should I have 3 blocking caps and then mix after ?

Here’s a write up on how to VGA :

https://chipnetics.com/tutorials/understanding-75-ohm-video-signals/

Looks like parallel 75ohm resistors going to GND from the input is good practice + a cap and 75 ohm resistor on output?

VGA OUTPUT examples :

If I understand this last one, three parallel 75ohm resistors makes a 25ohm resistor. 97ohms gets 80% of 3.3V gone before the 25ohm dissipates the rest so that there is 0.7V left for the 3 channels. For a 5V supply like mine, I’ll need to remove 86% of 5V to get it down to 0.7V.  A 160 ohm resistor then ?

VGA INPUT examples :

*EDIT Made the changes (RGB colors in to GND through 75ohm, one color through cap to bias + 160ohm and now there is no output…But maybe it was already broken at this point? Can test when new converters arrive.)

Looked at some VGA in/out boards I had in my possession and saw the following :

• H and V sync can go to a 74HC125 Line Driver / Buffer.
• Color returns can be conected together and grounded along with chassis.
• Examples of color pins going to grounded 75ohm resistors then on to blocking caps. Also colors to gates of transistors.
• Colors also going to video signal switcher like this : QS4A210 – 2-Channel 4:1 Analog Mux/Demux
• Definitely DO NOT ground pin 9 (which is 5V), as I have done in all previous boards…

****

An older HDMI to VGA converter broke so I opened it up to see if I could reproduce it. It’s an ALGOLTEK AG6201 which appears to be not accessible anywhere but the manufacturer’s website.

The alternative is using a video chip which can trasmit HDMI like this project : https://hackaday.com/2019/07/26/hdmi-from-your-arduino/ which uses a CH7035B HDMI encoder.

Alternatively I use the HDMI to VGA adapter and solder a D Sub Standard Male connector (https://www.mouser.fr/ProductDetail/TE-Connectivity-AMP/2301843-1?qs=rrS6PyfT74crws9wAQVNoA%3D%3D&mgh=1&vip=1&gclid=Cj0KCQjw27mhBhC9ARIsAIFsETE7Rp9JFGXhYFAXh_Z2YbQUB2NfHqO8rM7yPueb-T3yFiKbUMvJkOEaAtjJEALw_wcB) to the board.

***

I will be testing a pico projector and a VGA capture device soon…

***

Trying again with SPI SRAM

This code seems solid to me but I can’t go beyond 100Hz…

#include <SPI.h>
#include <SRAM_23LC.h>

// SPI bus can be SPI, SPI1 (if present), etc.
#define SPI_PERIPHERAL    SPI
#define CHIP_SELECT_PIN   8

/* Device can be:
 * 128KB: SRAM_23LCV1024, SRAM_23LC1024, SRAM_23A1024
 * 64KB: SRAM_23LCV512, SRAM_23LC512, SRAM_23A512
 * 32KB: SRAM_23A256, SRAM_23K256
 * 8KB: SRAM_23A640, SRAM_23K640
 */
SRAM_23LC SRAM(&SPI_PERIPHERAL, CHIP_SELECT_PIN, SRAM_23LCV1024);

// Additional SRAM chips
// SRAM_23LC SRAM1(&SPI_PERIPHERAL1, CHIP_SELECT_PIN1, SRAM_23LC512);

#define START_ADDRESS   0

//uint8_t buffer[BUFFER_SIZE];
//#define BUFFER_SIZE  320

char buffer[1000];
#define BUFFER_SIZE  (sizeof(buffer) / sizeof(uint8_t))

void setup(void)
{
  pinMode(2, OUTPUT);
  /* Without parameters, begin() uses the default speed for this
   * library (12MHz for samd, 14MHz for sam, and 4MHz for avr).
   * Note that SPI transaction support is required.
   */
  SRAM.begin();
 // SRAM.begin(8000000UL);      // or specify speed
  //Serial.begin(9600);
}

void loop(void)
{
  //while (!Serial); // Wait for serial monitor to connect

// Record a series of values
  for (size_t i=0; i < BUFFER_SIZE; i++) {
    //buffer[i] = byte(digitalRead(A2));
        if ( (PINC & (1 << PINC2)) == (1 << PINC2) ) { //PC2 is what we're reading
        buffer[i] = 0xFF;// pin is high
        }
        else {
        buffer[i] = 0x00;// pin is low
        }
  }
/*
  // Print buffer to serial monitor
  Serial.print("Write Block: ");
  for (size_t i=0; i < BUFFER_SIZE; i++) {
    Serial.print(buffer[i], DEC);
  }
  Serial.println();
  */

  // Write block
  if (!SRAM.writeBlock(START_ADDRESS, BUFFER_SIZE, buffer)) {
    //Serial.println("Write Block Failure");
  }

  // Clear buffer
  //memset(&buffer[0], 0, BUFFER_SIZE);

  // Read block
  //Serial.print("Read Block:  ");
  if (!SRAM.readBlock(START_ADDRESS, BUFFER_SIZE, buffer)) {
    //Serial.println("Read Block Failure");
  }

  // Print buffer to serial monitor
  for (size_t i=0; i < BUFFER_SIZE; i++) {
    //Serial.print(buffer[i], DEC);
   if(buffer[i] == 0x00){
     //digitalWrite(2, LOW);
      PORTD &= ~(1 << PD2);    // set pin 2 of Port D low
   }  
   else{
    // digitalWrite(2, HIGH);
      PORTD |= (1 << PD2);     // set pin 2 of Port D high
   }
  }
  //Serial.println();
  //delay(1000);
}

I just can’t manage to get the same level of control with an SPI device as with parallel SRAM and counters.

****

New board time 😀 ! Test new things but keep the plug and play idea from last board and make even more so. SPEND MORE TIME SANITY CHECKING THE DESIGN and double checking pull ups and downs.

Goals :

• How about using a 16Mbit SRAM to store 128MBits of data with only a few added components ?! The plan is a pair of shift registers to convert serial output from a comparator into 8 bits to be sent all at once to the SRAM and the inverse on the output side. I would need the shift register clocks to be 8 times faster than the SRAM I think?
• Make it so power (5V – with an LDO on board to eliminate possibility for accidents) can be shared with a double power jack. Reverse polarity protection.
• A fine and coarse threshold selection !
• proper VGA input and output good practices that will never harm anything sending video signals in or recieving signals sent out (blocking caps, 75 ohm impedence matching, Vref for top side of variable comparator bias!!, buffers for H and V sync!!, two cables close together!! and shielding – guard rings? – on the PCB for these traces!! different grounds for different parts of the VGA cable, use BNC connectors for RGB??)
• Raspberry pi as input VGA through converter which plugs into a male VGA on the board, add an OFF/ON switch to safely turn off
  
• pass thru VGA signal switch !!
• Have different clock cans to switch between?
• Extended Display Identification Data chip as a test?
• Have audio out option ?

Here’s the preliminary circuit :

From https://www.cs.unca.edu/~bruce/Fall11/255/Labs/Lab13AnalogInput.html

From https://electronics.stackexchange.com/questions/144530/circuit-for-a-coarse-and-fine-setting-potentiometer

****

As for PCB inspiration, perhaps something that evokes the computer video graphics card :

Rectangular, with metal bracket (these are called Computer brackets in the Circuit Board Hardware – PCB category of Mouser.fr. They come in low profile or high profile), fan, heatsink, memory bank in a row, name of the board somewhere, PCI connector

****

Here is my first attempt at simulating the logic :

The only tricky part was activating parallel load of the output register only once per 8 clock cylces.

This design includes a giant FPGA to control enables all broken out along the PCI-E connector (that could be played like a piano with an alligator going to GND) in time and also to match the aesthetic of the video card. It would feature a stunning 128 Mbits (16MBits SRAM x 8) of memory. Would be cool to have LEDs next to each memory which light up when that block is recording.

***

Building on the idea of making physical artefacts, Vivien Roussel had the idea of moving towards displaying the chassis of the computer along with these boards. There are loads of cool test bench computer cases that could be an inspiration for this :

****

Or a DDR SDRAM module as inspiration :

Here’s what it’s looking like in Eagle so far :

I still like the idea of a kind of piano controlling :

• 3x SRAM CS sel bits
• 3x COUNTER EN + individual RST

And of course :

• Threshold control (fine and coarse this time !)
• Clock DIV
• REC/PB

Here’s the board as ordered :

CIRCUIT DIARY :

• The fine and coarse pots appear to work very well.
• The clock divider works as expected. Though it might be interesting to be able to play with different frequencies too as it seems to be important to get the combination of sampling versus pixel frequencies.
• I checked and the serial clock is indeed being divided by 8 and inverted (albeit super noisy!) :
• The Overflow and CS signals appear to be working well (though I had a hard time soldering the resistor networks!)
• The !WR signal is as expected
• Possibly should have put pull-downs for the SRAM I/0 pins ?
• I should have made a timing diagram not just the simulation..
• The option to manually advance the OVERFLOW signals is cool because you can solder one SRAM and test only it without having to wait for its turn to come around !
• I have reached a problem : the 596 is not shifting the serial into parallel. I can see it trying (little mini signals getting through), but it is as if the I/O pins are being pulled low, but by what ? The SRAM ? I’ve confirmed we’re in write mode so they should be high Z. The Serial to Parallel converter somehow? But the I/O pins are inputs for this IC…Hmmm. Is it something to do with the open drain outputs (or the Schmitt trigger inputs?) on the 596 ? **EDIT : Had a 595 with the same footprint and substituted it, seems to be working now.
• So, the output is very stripey. I have removed the 75ohm resistor to ground and shorted the 100ohm to the output RGB pins. I’ve tried shorting the blocking cap and it makes things a tiny bit easier to see but overall it is barely legible as an image. I think it has something to do with the output parallel to serial conversion. Here is a sample of a capture :

• For some reason it can also work much better :

• I don’t understand how it is possible to see the screen while it is recording as there is no “pass-thru” option…. There is also sometimes quite a difference from what is somehow passing through while in record mode and what plays during PB mode. *EDIT*There is a noise issue, when the VGA input is plugged in there is static that is entering somewhere. Trying to locate it currently. *EDIT* it is coming from the VGA IN. Tried connecting a bunch of GNDs (digital GND, chassis GND, color return RED) but still getting nowhere trying to eliminate the noise.
• I ordered the wrong type of bracket, this one is for a double row VGA…
• I had an issue with SRAM D but then replaced it and all is good.
• I forgot to have a pre-amp before the comparator, this is essential otherwise you don’t get any in screen peaks and basically don’t see anything unless you’re really lucky. I used the Palimpsest.OS preamp and bias setup and it works fine.
• The tiny trimpots need to be replaced with actual knobs !!
• I forgot to add loop LEDs ! It would have also been cool to know which SRAM is currently recording.
• EVERYTHING IS WORKING I CAN’T BELIEVE IT. The solution was to just test everything with a simple ramp using the function generator and look at the play back. Then I checked the pins on the SRAM and saw funky signals for several address pins that looked like they were several signals being added together. Clearly when I soldered in a bunch more SRAM and there were tiny connections between five different address pins and an I/O that I did not notice. This was causing chaos. I found the connections and fixed them, now it’s recording just as expected and it’s so glorious. NOTES : I am using the op amp from Palimpsest.OS AND crucially, am connecting both Analog and Digital Grounds between the two boards and the VGA IN with VGA OUT.

***

While waiting for this board to arrive :

• Try different function generated patterns of hitting count 0 enable while recording on the 16Mbit version
• Test the 8 layer board ! *DONE*
  • Remove pin 9 GND and fix other issues with VGA in and OUT with VGA beakout PCB
  • Test on raspberry pi / computer IN *DONE*
  • Test feedback ! *DONE*
• Try mini projector *DONE*
• Try VGA capture device *DONE*
• Put restart button on rasbpi

*******************

*EDIT* It works with rasbpi when I connect only a color, GND, H and V syncs !! So much more convenient than previously.

• It might be cool to be able vary the mixing of the different channels
• The output image is quite faintweak, I think I should rexamine the resistors I put at the termination and maybe switch to B+W.
• It’s a bit muddy with several channels, would be cool to be able to filter that
• I need a path to feedback with a pot !
• Switched the output resistors to a 150ohm going to R,G,B and it works nicely.
• Dip switch hard to use without tool.
• Hard to see which direction switches are pointing in darker light

More technical ERRATA :

• Pin 1 of the 40MHz clock should be pulled HIGH to be enabled, not LOW as it is on the board !
• The THRESHOLD pot isn’t connected to GND on one side…
• I should have tied the CCLR (pin 10, which resets when pulled LOW) of the 590 to VCC with a 10K instead of leaving it floating connected to VSYNC. This made it malfunction.
• BIG PROBLEM : I ordered multiplexers (unidirectional) instead of analog switches (bidirectional) ! The ‘157 multiplexers mess with SRAM B’s I/Os when it is in READ mode (when the SRAM is outputing values on the I/O pins). I ordered a replacement that is pin compatible, the 74LVC1G3157 (DATASHEET : https://www.ti.com/lit/ds/symlink/sn74lvc1g3157.pdf?HQS=dis-mous-null-mousermode-dsf-pf-null-wwe&ts=1679316452048&ref_url=https%253A%252F%252Fwww.mouser.de%252F). EDIT* The new components work perfectly – everything is good !
• The Sync Clock IC is 3.3V not 5V…
• Image jumps around of course. When I try to record with the Burst AND IC which outputs !CLK, no writing can occur. I’m guessing this gate messes with the timing somehow? As a workaround I’m trying to connect the 4 AND’ed V SYNC counts to either the address counter IC Reset or to another reset somewhere. 
• Lots of noise on V SYNC, I should maybe have made the input and output VGA jacks right next to one another…
• Pin 9 of the VGA D-SUB 15 is VCC for the Display ID EEPROM chip – but I have it connected to GND !! In general I need to respect the rules around the different grounds and return pins in the VGA protocol and not just connect them all together. Hoping to fix this in the next version.

***

Thinking about making a board with a small 5″ screen / or a mini projector incorperated in it

Fabien suggests using an LCD driver from a normal sized computer screen for a smaller screen (but he says it will will in 16:9 format). The other option he suggests is to use an FPGA to control a screen directly with LVDS.

Artist Andreas Gysin’s LCD 1 from http://lcd.ertdfgcvb.xyz/

***

Just realized that I could have an raspberry pi using VGA directly from I/0 pins : https://fr.pinout.xyz/pinout/dpi#

****

Currently thinking the next PCB should be raspberry pi sending video through I/O (not through HDMI) and FPGA controlling SRAM. This would allow messing with the sequence of the memory recording / playback. Could make a compact version of this project (a kind of black box, deployable version) without many external components but with sililar functionality. I could test making the FPGA USB programmable board too. Of course it would also be programmable.

To get here :

• make the automated palimpsest.OS board
• make the simple FPGA VGA board

****

I am revisiting the SPI SRAM code with renewed patience, I actually wrote it first on paper !

Here is my simple buffer filling code first off :

const int buffer_size = 2000;  // Only 2K bytes of SRAM on the 328P
byte buffer[buffer_size];
void setup() {
  DDRC = 0b00000000;  // set PC2 as input pin
  DDRD = 0b00000100;  // set PD2 as output pin
}

void loop() {

  //  fill the buffer
  for (int i = 0; i < buffer_size; i++) {  // iterate through buffer
    for (byte mask = 0b00000001; mask > 0; mask <<= 1) {  // iterate through a bitmask
      if ((PINC & 0b0000100) == 0b00000100) {  // if input pin high...
        buffer[i] = (buffer[i] | mask);  // set this bit
      }
      else {
        buffer[i] = (buffer[i] & ~(mask));  // clear this bit
      }
    }
  }
  // read buffer back
  for (int i = 0; i < buffer_size; i++) {  // iterate through buffer
    for (byte mask = 0b00000001; mask > 0; mask <<= 1) {  // iterate through mask
      if ((buffer[i] & mask) == mask) {  // if bit in buffer is high...
        PORTD |= 0b00000100;  // ...write output pin high
      }
      else {
        PORTD &= ~(0b00000100);  // else, write output pin low
      }
    }
  }
}

I tried the mini projector but it didn’t like the signals I was sending it. I think I have to avoid intelligent interfaces that can decide to send or not along my signals. Wondering about the camcorder CRT viewfinder and if I should head back in that direction.

Here is a popular 4″ screen :

Inspired by the history of mounting circuits on wood with screws and wire, evoking John Cage’s prepared pianos. 

This iteration of the project is born of a few realizations :

1. VGA is an analog signal, it’s not digital.
2. The coolest effects are the simplest ones : XOR, HP and LP filters, comparators, etc. which can be easily made with discrete components.
3. A simple low frequency oscillator could control these effects with an LED > LDR voltage controlled resistor set-up. 
4. Two out of sync oscillators easily make a pattern that doesn’t repeat often and is difficult to predict.

Pedagogically and aesthetically I like this idea : it goes back to the basics of electronics, the history of electronics, and will show the materiality of video signals. This in contrast to the overly complex use of digital components to do basic modifications…

The three basic circuits :

*TESTED* This works (powered at 5V, with pull down 10K on input and the rest 1K and two BD135s) at lower frequencies (<100KHz) around 5V.  I added a 5K variable resistor (or an LDR + resistor) to increase the resistance of R1 and it varies the threshold !

*TESTED* Works using BD136 PNP, 10K for the pull down and 1K for the base protection. General purpose diodes. I replaced the pull down with a 5K variable resistor and got some messed up results in the MHz. Doesn’t need power – just takes it from the input signal ! (But VGA signal would need to be amplified in order to work. 

*TESTED* With a 104 cap and 5K variable resistor I can vary the filtering of a 5V function generator signal. 

****

OK we’re back to the original plan ! Here is the Palimsest.OS Rev.2 :

WHY ?

• This board is for the inauguration of the IFT at the DVIC. It has to demonstrate technical proficiency on behalf of the staff, and must run independently as an tech-art installation, modifying video independently day in day out. 
• Rev.1 didn’t work for microchip automation, this one should work smoothly(?). If everything works I could write code that executes different video manipulations. I also added selection LEDs to show the microchip doing its thing.
• This tests the 8 channel 1-bit WRITE/REWRITE memory idea (but not the more elegant SRAM + buffer idea of Fabien), with certain effects tied to certain channels
• Incorporates a simple to control XOR, comparator and HP/LP/BP filter into one board
• Has a stable clock setup with metal can oscilloscope, a gen lock IC, and V SYNC burst setup
• Tests an (expensive) programmable filter IC
• It is a test for a simpler, inexpensive 8 ch recorder board that could be a cool kit
• Does away with the ADC and all its pesky issues and trades it for a simpler 1bit “ADC”. 
• I’m also using 5V SRAM to avoid the headache of different logic levels (though this means I only have 4MB of SRAM versus 16MB).
• For testing purposes it can be soldered as a logic-controlled board or as a physical switch controlled-board. 
• Instead of having lots of jumpers for wires, I went for rotary switches to make things more plug and play. However this also means that there are fewer experminental tests that are facilitated (like disabling a single counter while recording etc.) that were possible on rev.1
• Can layer different recorded portions easily in theory
• Battery switch and edge potentiometers instead of knobs
• Theoretically could do feedback and echo tests with this board as it can read and write from and into memory simoultaneously 
• This board should be easier to work with than the previous stacked PCI-E motherboard design which made knob turning and mounting hard. 
• Instead of using generic octal logic ICs I went for more specific purpose ones.
• The board will be made at https://aisler.net/ instead of JLCPCB so I’m hoping for a really nice finish

Here’s a possible minimal installation with it :

****

PALIMPSEST.OS v2 ERRATA :

• Pin 1 of the 40MHz clock should be pulled HIGH to be enabled, not LOW as it is on the board !
• The THRESHOLD pot isn’t connected to GND on one side…
• I should have tied the CCLR (pin 10, which resets when pulled LOW) of the 590 to VCC with a 10K instead of leaving it floating connected to VSYNC. This made it malfunction.
• BIG PROBLEM : I ordered multiplexers (unidirectional) instead of analog switches (bidirectional) ! The ‘157 multiplexers mess with SRAM B’s I/Os when it is in READ mode (when the SRAM is outputing values on the I/O pins). I ordered a replacement that is pin compatible, the 74LVC1G3157 (DATASHEET : https://www.ti.com/lit/ds/symlink/sn74lvc1g3157.pdf?HQS=dis-mous-null-mousermode-dsf-pf-null-wwe&ts=1679316452048&ref_url=https%253A%252F%252Fwww.mouser.de%252F). EDIT* The new components work perfectly – everything is good !
• The Sync Clock IC is 3.3V not 5V…
• Image jumps around of course. When I try to record with the Burst AND IC which outputs !CLK, no writing can occur. I’m guessing this gate messes with the timing somehow? As a workaround I’m trying to connect the 4 AND’ed V SYNC counts to either the address counter IC Reset or to another reset somewhere. 
• Lots of noise on V SYNC, I should maybe have made the input and output VGA jacks right next to one another…
• Pin 9 of the VGA D-SUB 15 is VCC for the Display ID EEPROM chip – but I have it connected to GND !! In general I need to respect the rules around the different grounds and return pins in the VGA protocol and not just connect them all together. Hoping to fix this in the next version.

More Meta errata :

• It’s a bit muddy with several channels, would be cool to be able to filter that
• I need a path to feedback with a pot !
• Switched the output resistors to a 150ohm going to R,G,B and it works nicely.
• Dip switch hard to use without tool.
• Hard to see which direction switches are pointing in darker light

Oy vey ! I realized that I could just use an I2C RAM IC and save about a billion components. Here are the more plug and play simple boards I made in the aftermath :

Good news: The 328 works. 

ERRATA : I fried the logic chips with 5V :(. Resoldered new ones and looks good.  I think I need to be feeding in a signal that has already been digitized (like by a comparator). Otherwise I need to mess around with knobs to get the signal right around the threshold of the logic gates with bias setup. 

Good news: The 328 works. And I can see the effect of selecting different filters. I’m not sure why but it works best when the signal is coming in on A and I’m taking the output on B (or vice versa). I’ve also got a cap going from the output of the filter board before amplifying it again.

ERRATA: I ordered the wrong length of bussed resistor network. 

Good news: The 328 works. 

errata ^ Wrong footprint (and value!) for the digital potentiometer here… Will have to wait for the correct part to test this.

Good news: The 328 works and at least it produces an image !

errata ^ H SYNC and V SYNC plugged in to wrong pins on Arduino (should be PD3 and PB1 respectively).

Good news: The 328 works.

ERRATA : the PD pin (which enables ADC IOs when low) is pulled HIGH ! I resoldered it and now it’s working great. 

I chose a non PWM pin on the atmega to be the voltage control pin of the VCO… I soldered it to the nextdoor pin which can do PWM and all is good. 

ERRATA: I tried two chips, they both come up as unidentified FRAM when I have them speak on the serial running the demo codes…I should probably pull Write Protect (WP) HIGH just in case. Still not working…I will try replacing with a 23LC1024 serial SPI SRAM as it has the same pinout. 

***EDIT: Just saw this on the Adafruit website : “For the 4Mbit version, you should change this to: fram.begin(3)”…Still doesn’t work though.

I replaced with the 23LC1024 and am using the SRAMsimple libary which appears to work well. For some reason the digitalRead I’m doing in the setup is always returning 0 even if connected to 5V.

#include <SRAMsimple.h>
#defineCSPIN8       // Default Chip Select Line for Uno (change as needed)
SRAMsimple sram;       //initialize an instance of this class
/*******  Set up code to define variables and start the SCI and SPI serial interfaces  *****/
voidsetup()
{
uint32_t address = 0;                       // create a 32 bit variable to hold the address (uint32_t=long)
Serial.begin(9600);                         // set communication speed for the serial monitor
SPI.begin();                                // start communicating with the memory chip
  // And now the fun begins:
/**********Write a Single Byte *******************/
bool data = digitalRead(A0);                        // initialize the data
for(int i = 0; i <=5; i++){                 // Let's write 5 individual bytes to memory
    address = i;                              // use the loop counter as the address
sram.WriteByte(address, byte(data));            // now write the data to that address
    data+=2;                                  // increment the data by 2
}
/********* Read a single Byte *********************/
Serial.println("Reading each data byte individually: ");
  byte value;                                 // create variable to hold the data value read
for(int i = 0; i <=5; i++){                 // start at memory location 0 and end at 5
    address = i;                              // use the loop counter as the memory address
    value = sram.ReadByte(address);           // reads a byte of data at that memory location
Serial.println(value);                    // Let's see what we got
}
}

Not sure why…

*EDIT: Got the thing working with Fabien’s help !  

#include <SPI.h>
#include <SRAM_23LC.h>
#define SPI_PERIPHERAL SPI
#define CHIP_SELECT_PIN 8

SRAM_23LC SRAM(&SPI_PERIPHERAL, CHIP_SELECT_PIN, SRAM_23LC1024);

#define START_ADDRESS 0

void setup(void)
{
pinMode(2, OUTPUT); // where we write the recorded data to.
pinMode(A2, INPUT);
SRAM.begin();
}

void loop(void)
{
for(unsigned long i=0; i<128000; i++)
{
byte val;
if ( (PINC & (1 << PINC2)) == (1 << PINC2) ) {
val = 255; // pin is high
}
else {
val = 0; // pin is low
}
SRAM.writeByte(START_ADDRESS + i, val);
}

delayMicroseconds(1);

for(unsigned long i=0; i<128000; i++)
{
byte ch = SRAM.readByte(START_ADDRESS + i);
PORTD = ch;
}

delayMicroseconds(1);
}

However in this byte write/read mode the fastest I can get it going is 10KHz…The next step is to use this SPI tutorial (https://docs.arduino.cc/tutorials/generic/introduction-to-the-serial-peripheral-interface) and the SRAM datasheet ( https://ww1.microchip.com/downloads/aemDocuments/documents/MPD/ProductDocuments/DataSheets/23A1024-23LC1024-1-Mbit-SPI-Serial-SRAM-with-SDI-and-SQI-Interface-DS20005142.pdf) to operate in “sequential operation” mode where pages are ignored and its all just one big array. 

I have tried to do this but haven’t yet succeeded. I can successfully write and read from the memory with the code below..:

#define DATAOUT 11//MOSI
#define DATAIN 12//MISO
#define SPICLOCK 13//sck
#define CHIPSELECT 8//ss

//opcodes
#define READ 0x03 // read data
#define WRITE 0x02 // write data
#define WRMR 0x01 // write to the Mode Register

//modes
#define SEQUENTIAL 0x20 // 0100000 in Binary

byte clr;

byte address0 = 0;
byte address1 = 0;
byte address2 = 0;

byte data_to_write = 0;
byte data_to_read = 0;

char spi_transfer(volatile byte data)
{
SPDR = data; // Start the transmission
while (!(SPSR & (1<<SPIF))) // Wait the end of the transmission
{
};
return SPDR; // return the received byte
}

void setup(void)
{

pinMode(DATAOUT, OUTPUT);
pinMode(DATAIN, INPUT);
pinMode(SPICLOCK,OUTPUT);
pinMode(CHIPSELECT,OUTPUT);
digitalWrite(CHIPSELECT,HIGH); //disable device
pinMode(2, OUTPUT); // where we write the recorded data to.
//pinMode(10, OUTPUT); // LED
pinMode(A2, INPUT); // where we read the data from
// SPCR = 01010000
//interrupt disabled,spi enabled,msb 1st,controller,clk low when idle,
//sample on leading edge of clk,system clock/4 rate (fastest)
SPCR = (1<<SPE)|(1<<MSTR);
clr=SPSR;
clr=SPDR;

digitalWrite(CHIPSELECT,LOW);
spi_transfer(WRMR); // access the Mode Register
spi_transfer(SEQUENTIAL);//enter Sequential Mode
digitalWrite(CHIPSELECT,HIGH); //disable device
}
void loop(void)
{
//WRITE
digitalWrite(CHIPSELECT,LOW);
spi_transfer(WRITE);
spi_transfer(address0);
spi_transfer(address1);
spi_transfer(address2);

for(unsigned long i=0; i<128000; i++) // address is automatically incremented internally in the SRAM in this mode
{
if ( (PINC & (1 << PINC2)) == (1 << PINC2) ) {
data_to_write = 255; // pin is high
} 
else {
data_to_write = 0; // pin is low
}
spi_transfer(data_to_write);
}
digitalWrite(CHIPSELECT,HIGH);

//READ
digitalWrite(CHIPSELECT,LOW);
spi_transfer(READ); //transmit read opcode
spi_transfer(address0);
spi_transfer(address1);
spi_transfer(address2); // 24 bit address in three parts (this could be a problem)

for(unsigned long i=0; i<128000; i++)
{
data_to_read = spi_transfer(0xFF); //get data byte
PORTD = data_to_read;
}
digitalWrite(CHIPSELECT,HIGH); //release chip, signal end transfer
}

…but when I do this in chunks with loops it doesn’t appear to work. I’m not sure if it’s because I’m reading the value of the pin during the writing and if I should perhaps do this before with a buffer array and then just read from it ?

OVERALL ERRATA : I also need some kind of power board that distributes 5V and 3.3V 

***

On the back of the boards I tried an experiment using the bmp import ULP in Eagle. Not sure what the results will look like :

   An

**** 

I also starting thinking that I should probably look at more existing DIY and pro analog video synth circuits…

A collection of great video synthesizer schematics resources : https://scanlines.xyz/t/diy-resources-file-system/224

Here are some of the ICs (that are still being manufactured) that I haven’t work with before that appear in several designs :

• Resettable and retriggerable Monostable Multivibrators : https://assets.nexperia.com/documents/data-sheet/74HC4538.pdf
• High speed diff comparators : https://www.ti.com/lit/ds/snosbj5c/snosbj5c.pdf?HQS=dis-mous-null-mousermode-dsf-pf-null-wwe&ts=1676232730602&ref_url=https%253A%252F%252Fwww.mouser.fr%252F
• Video Fader IC: https://www.analog.com/media/en/technical-documentation/data-sheets/12516fa.pdf
• Graphic EQ display filter : https://www.sparkfun.com/products/10468

To divide a signal into 8 different bands (if you skip the MUX at the end) :

Here’s a simple implementation with a 4051 analog mux at the end :

This worked after I sorted out that the Atmega 328 reset was pulled LOW all the time – so it programmed fine but never did anything after that. I also removed the op amps which were supposed to follow the selected thresholds, I connected the top and bottom directly to the pots in the end. I tried slowly switching between bands at half a second and also faster at 50ms. Both as expected.

And I’m revisiting all kinds of combined capacitor + switch circuits which move tiny charges around based on signals  :

• sample and hold 
• bucket brigade
• comb filter 
• switched capacitor circuit

 I have made this bucket brigade “delay” with 50 microchip tunable (variable) 100-200pF capacitors :

I am now curious about some other capacitor switching circuits like this Comb Filter : https://en.wikipedia.org/wiki/Comb_filter which somehow “provides response” at different multiples of 1KHz depending on 3 bit code. All the caps are the same value.

Here is another circuit design for the same function :

****

For the FPGA board, I’ve ordered an iCE40HX1K development board and am currently planning to test some basic VGA signal generation. The next steps could involve basing a design off of the OLIMEX dev board design (https://github.com/OLIMEX/iCE40HX1K-EVB/blob/master/ICE40-1KEVB_Rev_A.pdf) which already has SRAM and VGA OUT along with code on the internet (which I would follow closely for the first iteration). I would alter the board to be able to program directly via USB using the components from the Ice40 stick ( https://www.mouser.fr/new/lattice-semiconductor/lattice-icestick-kit/), like a fancy new FTDI chip, so I could stay within the Lattice software for my first steps. 

Compared to the VGAX, the FPGA could generate signals much faster (being clocked with a 100MHz crystal versus the 16MHz of the Atmega), it would also be producing signals based on a a different coding paradigm (I have no idea what that would mean in terms of images), and because it has around 90 I/O it could also work with super deep colors using only a R2R ladder. The possibility of using an SDRAM is so cool but it seems hard to implement, with SRAM being much simpler to interface. The OLIMEX has only 512KB of SRAM, so I couldn’t really record a lot with it. 

****

Here is my process for the FPGA programming so far :

1. I signed up for an account at www.latticesemi.com.
2. I got a licence for iCEcube2, put it somewhere easy to find and took note of the directory, and downloaded iCEcube2 and the Lattice Diamond software from here : https://www.latticesemi.com/en/Products/DesignSoftwareAndIP
3. I plugged in the iCEstick and it blinked in a circular pattern. I also checked that it had a port under Device Manager (it had 2!). 
4. I went into iCEcube2 then to Help > Tutorial to open a pdf called “Implementing the Design” and followed the following steps :
   1. Start new project (iCE40, HX1K, ?TQ144?)
   2. Add Design file iCElab.v and Constraint file iCElab.sdc and checked the Device Info.
   3. Run Synplify Pro Synthesis
   4. Select Implementation
   5. Add constraint file iCElab.pcf under Import P&R Input Files.
   6. Run Placer
   7. Check the Floorplan, package view, timing analysis, power estimation
   8. Generate the bitmap (.bit and .hex files) which is saved wherever the project was saved. (For instance C:\Users\Jonah\Desktop\FPGA LATTICE DEMO PROJECTS\quick_start\quick_start\quick_start_Implmnt\sbt\outputs\bitmap).
   9. Here is what everything should look like once finished :
   10. 
5. I then transitioned to Youtube for a detailed explaination of using Diamond Programmer with the iCEstick here : https://www.youtube.com/watch?v=Df9k1T0bHmA&ab_channel=Dom
   1. Launch Diamond Programmer and take the default options (or click scan and take those)
   2. It will mistake the board for a JTAG interface and give the following errors : “Failed to scan board”, “Scan Failed – Creating Blank Programmer Project.”
   3. Now change the Device Family to iCE40, the device to iCE40HX1K, and under Program enter the following information :
      1. Change Access mode to SPI Flash Programming and now some other options appear. Select > Vendor: Micron, Device: N25Q032, Package:  8-pin VDFPN8
      2. Now load the bitmap (.bin) file and check that it has a non-zero datasize :
      3. 
      4. Click OK and then click the green traffic light on the next to top row of icons. You should then see a completion message and have the program on your board :
      5. 
      6. Presto !

Just for info :

For the actual pinout of the ice40 (which you can change in Pin Constraints Editor):

Generating your own .v file, you can open Notepad++ and paste :

module AND( input A, input B, output Y ); assign Y = A&B; endmodule

***

Here’s what ended up getting presented :

Here is the text I made to go with it :

My takeaways :

Do something simple, and humble, but try to do it well. Trying to do too many things, or a “universal” thing, or a multi-functional reprogrammable thing is really ambitious. This has happened to me before :

• At the Barilla Hackathon (the team that did the best made a simple lunch surface, it was simple but really well made and designed). 
• With my solar robot project (the one that was supposed to run on solar energy and no battery, interact with other robots, and possibly build a structure)
• With my original solar sunflower design that was supposed to look super intricate.

Making a machine that works for a demo is the highest level of challenge. It requires you to master the functining of the machine to a high degree to be able to fix it and adapt in changing conditions. It you do something simple, you have a higher chance of being able to do this.

It would have been important to realize that the place this was to be shown is a corporate environment, and that my interest in the bodge / bricolage would never have found its place here. The corporate mentality is shiny, new, pro-tech, and “impressive”. I should have understood this before taking the project. 

The simple, distilled, purified, humble and clear idea from this project was the wooden-mounted electronic circuits. This would have been in line with my “design research” interests, my aesthetic.

If I were to make a complex machine like the one I had in mind for this expo that would have worked, I think I would have to change the following things :

• Generate my own VGA signals. For plug and play things, generating this in software seems so much easier because you are the one making it and you have control over what is being produced. 
• Figure out, once and for all, the story around shared grounds and blocking caps, and bias pots, and voltage in and voltage out levels, for different modules. Also, 75ohm resistors and small caps before VGA out ? Should I just get a VGA driver chip that works? (EDIT: Here is an explaination of how to calculate the output impedence for VGA cables : https://hackaday.io/project/18682-pic-graphics-demo/log/49786-vga-interface)
• I would need to figure out what makes the VGA monitor turn off (is it sending something it doesn’t consider a video, or a voltage level that is too high?)

I think the alternative, which would be showing pre-recorded videos, is uninteresting for a performance. Another key ingredient I think is having designers / artists to help me review the project regularly (like in design school). It should also be really clear to me if it is my design project or a commission (in which case I’m an engineer I guess?). I should also get clear right from the begining next time what are the conditions of the final thing – where will it be, what are the goals of the person commissioning the work, etc.). I should probably only work with people who share my interests and aesthetic ! 

I think I have to acknowledge that I have an extremely constrained working process that is highly method driven. I am not focused so much on the end product directly. My friend suggested I was over constraining myself. Basically there is a confusion between whether I’m using technology to stumble upon unexpected things, or whether I’m using it to make something that works. To work efficiently on things would work well would require time developing the things that must work well, and an organized, systematic working practice. I MUST ORGANIZE MY ELECTRONIC PARTS to make this process more efficient.

Also : all the intense pressure and hardcore work streaks I put in DID NOT HELP THE FINAL PROJECT – I can’t even think straight or debug basic circuits right now :(. It would have been better to perhaps start working on the final thing starting on day 1, with the EASIEST, SIMPLEST, AND MOST LIKELY TO WORK PAINLESSLY solutions. 

Another key question is what is the output, and who is my audience ? I need a way of mesuring my output and comparing it. 

• Am I making art for people who consume art ? (then I have to move towards very simple projects and focus on their EXECUTION while photographing everything super well for my PORTFOLIO)
• Am I making “design research” papers/talks for academics and people who consume this ? (then I need to WRITE about my research)
• Am I making open-sourced electronics kits for hobbyists ? (Then I need to spend time ENGINEERING working kits that people would be interested in making)
• Am I making workshops for designers ? (Then I need to come up with simple exercises for workshops?)

And am I doing several of these things simoultaneously ? I think doing any one of them well first could take a lifetime already ! My friend suggested projecting five years in the future to where I would like to be and building backwards from there. I think I would most like to be a teacher who does art/design research in the form of expos, articles and classes (a bit like Andrew Witt at the GSD).

********

Where I would like to go from here :

1. Test my basic FPGA VGA board. What can it do with video ? Possibly make another pro version (USB programmale, nicely laid out, SRAM). FPGAs feel like the future because they are good a processing video in parallel, and because coding them is essentially like building 74 series logic circuits but without all the soldering. It could also lead to some cool machine learning experiments later on..
2. Test my automatable SRAM 4MB board. What kind of automatic looping can it make?
3. Try to get the SPI SRAM board functioning (it is so simple it would be perfect for a video sampling workshop). It would be cool to see what kinds of images it produces. It works at 20MHz, it would be perfect !
4. Get Spaghettini working with aluminum board (just avoid going through-hole) – this is the simplest way to generate cool simple memory based video !
5. Have another stab at presenting my work as an art installation at my show end of march at La Générale. 
6. Try the bucket brigade and digitally controlled pot boards

*******

After my colleague Fabien told me about EDID EEPROMs, I am thinking it could be possible to mess with the memory of this EEPROM that communicates with the computer sending VGA signals and create some interesting glitches this way : https://en.wikipedia.org/wiki/Extended_Display_Identification_Data

Also check out these types of RAM : 

• https://en.wikipedia.org/wiki/Dual-ported_RAM
• https://en.wikipedia.org/wiki/GDDR_SDRAM

And this keeps coming up when looking into controlling screen rows and columns directly : https://en.wikipedia.org/wiki/Low-voltage_differential_signaling

Check out no input mixing and electro-acoustic musique concrete, and machine exorcism. 

Check out universal LCD driver IC RTD2556 on boards like this :

***

It looks like I could build my own HMDI to VGA converter with two AD ICs : https://www.analog.com/en/analog-dialogue/articles/hdmi-made-easy.html

I could combine this with a new board that uses a bunch of SPI SRAM memory chips controlled by arduino to approximate the 7 channel 4MB recording and mixing board I made. 

I could also put a rasbpi zero with just power, an SD card containing videos and an HDMI mini out. For the Raspberry Pi I made the HDMI hot pluggable (hdmi_force_hotplug=1) and put a bunch of low res mp4 videos in the boot SD card which are accessible.

 This circuit is a next version from the video synth. 

Some ideas from how this installation could look like :

Messing around with my last synths, here are some circuits that I want to be able to reproduce with my new synth :

Here are some ideas of how the circuit could take form :

A Nintendo gameboy catridge teardown :

Some sketches of possible configurations :

*******

I am currently splitting the project into two parts : 

PART 1 : A series of independent transforming modules, VGA IN/OUT with screens, and oscillators with patch cables.

PART 2: A board called palímpsêst.OS which is a rack (or archive) of several 16MB memory modules. 

***********

Palimpsest.OS

Each memory will share the same power (5V, 3.3V, GND), timing CLK signals, control signals (to enable/disable counters, buffers, RAM, ADC etc. and to RESET things). All this can be automatically controlled by an microchip which can turn on/off these memory banks individually in time. Despite this there will be basically all the components on the board to make it function independently and, most importantly, test and debug it’s functioning. 

Just like for the previous memory board, the following parameters will be modifiable :

• the duration of the recording and playback,
• the sequencing of addressing this memory,
• the amplification of the incoming and outgoing video data,
• the sampling rate and sampling pattern of video recording and playback,
• the bit resolution of the recording and playback,
• the continuity of the above processes or the frequency of their interruption

I have corrected the errata from the previous 16MB memory board, removed jumpers (as this board will be made by JLC PCB), added a ground plane, made it more compact (by removing the burst record functionality, level shifting, and having two layers). I also added a battery so that memory is persistent as long as the battery has juice. The main work however has been breaking out pins to a bus which can be controlled by a microcontroller. There is now the possibility to have 3 memory boards A,B and C, and to control their recording and playback, and all the parameters of these two things that can easily be controlled, in time. 

With these boards it should be possible to take an input, record it, then play it back and mix it with the input through a feedback pot. Because this can be done by three memories, they can also record their respective outputs and layer without any mixing with the VGA . 

*****

01/12/2022 UPDATE :

So far debugging: For some reason the ADC is not spitting out anything, regardless of what I feed it. I changed the input op amp and it had no effect. Previously to soldering the ADC everything seemed to be working…As far as I can tell the memory is working and all the bias pots too.

ERRATA :

-The direction pin of the 245 buffer connecting to the R2 ladder is wrong – it should be HIGH instead of LOW.  To temporarily correct this involves jumping the DIR pin to VCC – AND CRUCIALLY – to ALSO disconnect this pin from GND unless you will have a short.****

-Why on earth did I connect all the pins without dip switches (ADC EN, 1/0 0-7, etc.) from the memory boards together ? This makes it impossible to record on one board and not on the others. I cut the non-DIP’d traces and it seems to work. 

-the LED needs a current limiting resistor or it just explodes.

-one switch for master record (WR EN and ADC EN)?

-I should follow the ADC1175 instructions and isolate the DGND and AGND with caps. 

-Should have an input pin and 5V pin for testing on board.

-I should add the right footprint for a big capacitor at the input of the ADC (I forgot and put a 0.1uF which didn’t work).

-It would be super cool to have a coarse and fine knob (and or a super precise pot) for the VCO for instance on the base board. 

-I should take the classic gameboy battery footprint.

-There isn’t an extra pin so I can send V SYNC both to be frequency divided and pass it on to the VGA out. 

-The populated side of the memory PCB is facing “backwards” with regards to the base board…

-The LDO pinout on the base board is wrong

-I can’t plug in standard jumper headers to the PCIe breakout pins because they are a different diameter

-I tried hard syncing the VGA’s H Sync with the 4046 ( see text in description of video here : https://www.youtube.com/watch?v=S694YY7sJMw&ab_channel=drumasaurusrex ). It only works with the V Sync but that’s too slow. I can’t get a stable signal out, it looks super wobly at high frequencies.  

*****

TESTING THE PALIMSEST.OS

• Not sure why but it seems like I can’t record only on one board when multiple boards are connected. I have to disconnect all but the board I want to record on to get a recording onto it. *EDIT* Because I connected all the non-dipped pins from the boards together via the PCI-E bus…
• It would be super cool to be able to send different clock signals to each board. I should maybe not have made the same CLK hardwired to each board. 
• It’s not possible to turn the knobs when then three boards are plugged in at once because the pot shafts are too long. 
• Not sure exactly how the battery is working, it seems like it can “remember” something for a few minutes at least. 
• It’s hard to palimpsest various things together – You have to get one board all calibrated, then send it something from another calibrated board, record it, then rewrite to play it back. (I am hoping the new 8 channel 1 bit device makes things easier). 
• I can’t automatically have things read or write currently, not sure why it’s not working…
• I can’t echo with this board because I can’t simoultaneously read and write. That said I can mix a recording with live channel and then record that together into a memory and begin layering. 
• I would like to have the image stay stable instead of always jumping everywhere. 
• Dephasing the ADC and RAM clocks makesa large variety of nice patterns on the output !
• It would be nice to be able to count up and down and do that to 4 bits in the middle of memory !
• remember to connect GNDs if using memory board with analog f(x) for example
• Trying to hard sync with h sync and cd4046 based on these links (https://www.renesas.com/us/en/document/oth/tb476regenerating-hsync-corrupted-sog-or-csync-during-vsync and https://www.youtube.com/watch?v=5VymS65eefo&ab_channel=drumasaurusrex)… I think the solution might be an oscillator in a can (with 4 not 2 leads), which I can then divide. (I can still have a free style VCO with knob to control the sampling of the ADC though !)
• Works great with a four lead crystal oscillator can and the f divider – a very clean image that doesn’t warp ! You can still use the knob controlled high speed VCO to trigger the ADC and it’s a nice combo. 
• *****WOW – feeding in a quartz can 10MHz into a frequency divider (and sending diff divisions to the SRAM clock), and hooking up V Sync directly to the reset, produces a really stable image that doesn’t slide left or right !!!****
• ***ABOVE ALSO WORKS WITH H SYNC AT LOWER FREQUENCIES – SOOO COOOL : D !!
• I’m not able to use MOSFETs or transistors to reliably automate the switch from REC to PB for some reason. I’ve even tried using an optocoupler to isolate the arduino and also tried using and AND gate as a buffer with the WR signal but neither work. I think should use mechanical relays to get around this problem or just avoid it all together by having Arduino send the CLK and WR signals in the next version. 
• Tying differnt oscillator cans (10MHz, 12MHz, and 40MHz) 12 is nice because it doesn’t jump too much on my screen resolution (800×600). At 1280×720, 10MHz is nicest. 
• I did a proof of concept for the 8 track recording and rerecodording idea, it seems to work though there may be a bit of interference from neighbouring channels on one another ? Not sure how I would try to isolate them from one another but some bleeding might actually be cool ?
• I tried doing a feedback recording (recording a mix of a play back and a live feed) and had no success. Not sure why this isn’t working.

***********

Realizing that this whole massive multi-module thing could be made with just one memory module having feedback !!! That or a simple echo IC like this one I ordered (BU9253 : https://www.mouser.fr/datasheet/2/348/rohm_semiconductor_rohms16891-1-1742621.pdf ) :

That said the delay is only 8Kbits and it’s designed for audio.

*****

Analog Functions Board :

Trying to remake the previous analog functions board but at JLC and as pro-style as I can. The general idea is to make a bunch of op-amp circuits that modify video in various ways and that can be combined with the logic modification board to make a completely full suite of electronics video transformations. Not sure yet how they could be automated.

Fixes from previous esceptionally newbie laser engraved version :

• +15/-15V supply for all the op-amps using the handy ICL7660 negative voltage generating IC will hopefully solve many issues.
• Using normal general purpose op amps in addition to super fast video ones 
• Having bias pots at the inputs and outputs to sort out any different in offsets. 
• Doing more research to get better circuit designs, notably looking at the Analog Thing, The Hackaday Logic Noise Series, Rod Elliott’s active op-amp series.
• Making things less noisy with : seperated AGND and DGND, caps near op amps, following suggested board layouts, 2 sided board with GND plane (!)
• Tying to take into account impedence matching with 75ohm VGA camble at the input and output and testing a specialized video line driver IC
• Making op amp board with the possibility of automating thier switching / pot levels ?
• Adding over-amped fuz circuit, phase-shifter, and various filters (LP, HP, BP, Notch), and adding a reset to the integrator circuit. 

I think the theme of this board, especially seeing as I have 25 of these TL074 op amps, is showing the diversity of flavours (and range of sometimes exotic circuits) of the history of op amp filters, arithmatic, etc. circuits. I plan on highlighting the names (and dates?) somehow.

The idea has clarified now, it will be a grid of 24 different op amp circuits in a 6 by 4 grid with the name of each circuit and a letter/number identifier. At the top will be all the power, VGA in out and bias amps.

I collected the circuits from various places (AoE among them) but especially from Rod Elliott’s write up on active filters (which you can access with Internet Archive) : http://sound.westhost.com/articles/active-filters.htm

I am most excited about the combination of digital and analog – like in the switched cap filter, sample and hold, resettable integrator, and demux amp circuits. Being able to modify the functioning of am amp with digital signals (even with a tunable capacity and voltage controlled potentiometer) seems to offer really cool potential. This being combined with SRAM could be a really cool composite project.

ERRATA :

• VCCIO and GND directly overlapping on top layer  (near A2/A3) :/
• the preamp in and out and misaligned 
• Should have included blocking capacitors
• VGA not being recognized by my computer with driver chip 
• Should have included an inductor circuit
• awful humming from the negative 12V generator
• not enough room for 220uF caps for the video driver on board
• some kind of “pass through” switch would be useful to show what the input looks like
• the driver IC can only accept one color for some reason…I should not include it next time
• the female – female jumpers are not reliable and lead to weak contacts…maybe going towards jumpers?
• The thing is long to set up – it’s not plug and play and is finicky for demos
• Learn about the safety of hot plugging
• The Voltage Control works a litte, with a 1k8 resistor and picking the right voltage range. But it is not reliable, I should move to pot ICs for the next version. 

• A0  with a 200uF cap after the final amp has some filtering output
• A1  just tears the left side of the screen
• A2  nothing happening
• A3 varies nicely with different frequencies, though sometimes just looks like it’s “adding” frequency pattern to input
• A4 I think the original comparator design (with 1K resistor going to VCC and pot with middle shorted to GND going to GND is correct and this one wrong)
• A5 same note as above, but preamp in and upper seem to work. Perhaps the best way to get abstract forms from input super easily. 

• B0 Not working…
• B1 nice filtering !
• B2 needs blocking cap on output or else produces nothing. Goes from filtering to almost comparator like behaviour.
• B3 needs a cap on output and >20MHz to produce anything, no relation to input though ?
• B4 creates a cool zebra repeating effect at one extreme
• B5 great filter !! Both knobs do things and there is great range.

• C0 nothing cool happening here…Seems just to pass on a modified version of the digital in signal ?
• C1 top knob needs resoldering. Only does stuff when top knob fully to one side then behaves a bit like A3 but can go down to low frequencies on digital in.
• C2 Cool zebra like filtering (like B4 but messier and less repetitive.
• C3 nothing happening…
• C4 faintest image at one extreme
• C5 nice filter (like B5) ! Only top knob seems to do cool stuff though. (Other knob goes haywire at one extreme).

• D0 barely the faintest image at low frequencies…
• D1 the HP inverts the input !
• D2 Does add when the knobs are set right. I put a cap on the function generator input.
• D3 Does kind of subtract ! Can invert or not.
• D4 makes a banding across the screen, not sure what effect the 3 binary inputs have…
• D5 doesn’t really work but with the second multiplier input floating you can touch it and send the thing into an overdrive momentarily. 

*********

Notes from Museum visits :

void setup() {
pinMode(13, OUTPUT);
pinMode(12, OUTPUT);
}

void loop() {
//WRITE
PORTB = B11101111; // CLK goes LOW/HIGH
PORTB = B11011111; //WR goes HIGH/LOW
}

unsigned long startMillis; //some global variables available anywhere in the program
unsigned long currentMillis;
const unsigned long period = 1000; //the value is a number of milliseconds
int WRState = HIGH; // the current state of the WR pin

void setup()
{
pinMode(13, OUTPUT); //WR PIN
pinMode(12, OUTPUT); //CLK PIN
pinMode(11, OUTPUT); //ADC EN PIN
startMillis = millis(); //initial start time
}

void loop()
{

if(WRState == HIGH)
{
currentMillis = millis(); //get the current "time" (actually the number of milliseconds since the program started)

//WRITE TO SRAM
PORTB = B11101111; // CLK goes LOW/HIGH, ADC_EN HIGH
PORTB = B11011111; //WR goes HIGH/LOW, ADC_EN HIGH
     if (currentMillis - startMillis >= period) //test whether the period has elapsed
     {
      WRState = !WRState;
      startMillis = currentMillis; //IMPORTANT to save the start time of the current LED state.
     }
}

if(WRState == LOW)
{
currentMillis = millis(); //get the current "time" (actually the number of milliseconds since the program started)

// READ SRAM
PORTB = B11100111; // CLK goes LOW/HIGH, ADC_EN LOW
PORTB = B11110111; //WR stays high, ADC_EN LOW

     if (currentMillis - startMillis >= period) //test whether the period has elapsed
      {
       WRState = !WRState;
       startMillis = currentMillis; //IMPORTANT to save the start time of the current LED state.
      }
}
}

I want to continue messing around with magnetic media (audio cassette players/recorders, floppy disk drives, video camcorders) and try to get them recording and playing back video.

Here is some inspiration :

From the timeless Hardware Hacking manual. The suggestion is to use a high gain amplifier to hear the results of the tape pickup. :

A very cool project putting video onto a cassette :

https://www.ubergizmo.com/2020/04/audio-cassette-tape-used-to-capture-video/

From this reply : https://electronics.stackexchange.com/questions/108907/create-input-jack-from-tape-head

“You can use the continuity tester to check for the ground lead. This should be connected to the metal shield of the head, you can leave it unconnected. You’ll want to connect the other two wires to your two inputs”

From this site http://stevecoates.net/walkman/ :

This https://makezine.com/projects/turn-old-walkman-scratchbox/ Make Magazine article connects simply :

Some very cool experiments with a disconnected tape head :

And a custom loop tape :

**************************

I began testing a bit, it looks like I can both see and hear the audio signals from the tape (yellow is R?, blue is L?):

It’s most audible right near the end (the hum is the tape cassette motor spining) :

*****************************************

The method is just to power the cassette rotating motor with around 3.3V, then hook up the red(R?) or white(left?) to a probe or audio in for an amp, and then the black (GND) – which looks like it’s connected to two pins – to GND.

The next step would be to try to amplify with a high gain op-amp circuit ? And then to begin trying to write ?

UPDATE :

Might be easier to work with the electronics already present on the board, learn how it works, desolder it and then put it on a breakout board to mess around with? Here is one of the simplest ICs I found on one of the dissassembled tape decks in an easy to solder SOP16 package:

I could order a series of boards like this to make tests with them :

UPDATE:

I plugged in the little audio amp into the Audio out jack of the device while I touched different pins on the IC. I found that the large slide switch on the back switched from REC to PLAY. I found that during REC mode the pins that caused the most amplification were the MIC IN and EQ IN. In PLAY mode I found the most important pin for producing output on the AUDIO OUT was LINE IN.

I also tried connecting the little speaker amp to the REC OUT, LINE OUT while I touched various pins. 

I was unable to amplify the tape head signals however with any of the various combinations I tried. I will try the other tape cassette circuit boards to see if I have any more luck, and also test the 2.5W power amp from Adafruit. Ideally I would be able to take an input, amplify it, send it to the tape head, then read it back by reversing the sequence after rewinding to the same section. This should also work with a strip of tape taped to a desk that I can manually run the magnet head over (right??). 

Once I’m able to do this, I want to try the same thing (amplify an analog signal, write it to the disk through the heads directly, then read the analog signal back off it) with the Floppy Circuitry. 

*************

A great VCR technical reference : https://www.wikiwand.com/en/VHS

I got my hands on a VCR, took it apart and broke out the cable coming from the helical read/write head.

It looks like there is one little board with all the drivers for the various motors. Might be able to control it. (See this video : https://www.youtube.com/watch?v=4F7xJOb32GI&ab_channel=LifeOfDiy). I’ve got a BA6878EFV 3-phase motor driver for VTR capstan, datasheets available online. It looks like you need to plug in GND (3), 5V (2), and then connect EC(7) and HYS OUT (9) together.

So far I haven’t been able to pick anything up on the oscilloscope from moving the tape across the print heads while listening in to various output pins.

https://www.wikiwand.com/en/VHS#Media/File:Medion_MD8910_-_VHS_Helical_scan_tape_head-8601.jpg

There appear to be two video heads (with two wires each – one wire for each electromagnet) and two audio heads (with one wire each) making a total of 6 wires with 1 dummy. It looks like the pinout is the following :

1. Video Green 1
2. Video Red 1
3. Video Green 2
4. Video Red 2
5. No connection (shortened turn)
6. Audio Red
7. Audio Green

It seems like others have two shortened turns to help isolate signals from one another.

I measured the resistances between the output pins:

1. grey 
2. white
3. blue(1)
4. green
5. yellow(1)
6. orange
7. red
8. blue(2)
9. yellow(2)

The following are connected :

Looking up the chip LA71750 ( Video and Audio Signal-Processing IC) – on the right in the image below – and the LA7264B (Audio Signal-Processing IC) – on the left – and checking out the datasheets and inspecting the PCB, looks like the following are the important connections :

From the LA71750 datasheet :

Would appear possible to make this pinout diagram :

I have tried connecting pins to the oscilloscope while moving the tape head, but even at 10mV level at various time scales I can’t see anything. 

UPDATE : Just seeing now that this chip takes control data in the form of I2C. It would be super hard for me to desolder the chip and make my own controller with it as a result.

******************

I have tried amplifying and sending 20V signals at various frequencies. 

Turning to more research for answers, check out these links :

Article about audio sampler made from floppy :

https://nime.pubpub.org/pub/uh76shf0/release/1

Video made from floppy :

Freespin is a demo made for the Commodore 1541 – no, not the computer, just the floppy drive

For more tech info about floppy heads :

http://forums.openmusiclabs.com/viewtopic.php?f=11&t=92&sid=9a4c3a6763f9bc02426c9d3910187e70

******************

From this reading break I think the following things should be attempted :

-with a >2W class D amp can I push some signal onto the tape that I can then read ? (Just afraid that it won’t be fast enough for video signals as it is made for audio signals ? Perhaps a high power high speed amp is even better?).

-I could get the same preamp LA IC used in the concentric sampler paper.

-Everyone seems to say, “try different combinations with the R/W heads” and “check continuitiy” and apply the signal to continuous wires. 

-I could try adding the bias oscillator to the signal I’m trying to R/W?

-I should get a super strong magnet for testing purposes

***********

Looking at my floppy drive, I found the following CX20185 chip which is a Read/Write Amplifier for Floppy Disk Drive.

It looks like the pinout is the following :

It looks like I could read the Preamp Out pins to read from the floppy. I’m not sure how I could yet wright to the floppy without giving data to the logic on the driver.

Here is me figuring out the pinout :

I turned on the floppy LED I have by connecting the sixth pin next to the stepper head motor to the GND, and turned on the central motor by connecting the 8th pin to GND and plugging in 12V as well :

When I listen in to READ DUMP A or B I can see voltage when I spin the disk manually (when I plug in the brushless motor it no longer responds to spinning):

When I listen in to PRE OUT A or B I can see the normally high voltage go down and vary :

Meh. 

Some stuff about data degredation :

https://fr.wikipedia.org/wiki/The_Disintegration_Loops

Project Kryoflux – Part 3: Recovery in Practice

******

Suggestion from research engineer at DVIC for the previous experiments:

-For the floppy, look at the input from head (but oscilloscope will probably mess this up), preamp, and digital out (READ OUT – which should be connected directly to the chip I have the datasheet for) at same time. 

-Basically you’re not going to see anything on the oscilloscope when looking at these electromagnets. It’s all in the very sensitive amp – so all the more reason to use the amp that comes with the device !

-Is the preamp chip IC I am looking at even enabled ? Check POWER ON.

-Try the floppy pinout here : https://old.pinouts.ru/HD/InternalDisk_pinout.shtml

-For the VCR, get the thing plugged in and functioning as it was in the beginning. Observe it first, then try to intervene (you’ll never be able to reinvent the thing from nothing !)

****

Listening to the DATA READ pin 33 while the disk is spinning :

****

UPDATES:

I learned from watching this (https://www.youtube.com/watch?v=DdMOGvKjrfk&ab_channel=JeffHxC2001) that the way to read is to sync the oscilloscope with the INDEX pulse. The Difference Out pin is the one being listened to in this video.

I learned from looking more into the floppy interface that the Head Select (32) is HIGH for BOTTOM and LOW for TOP head. I also learned that Floppy Write Enable (24) is HIGH to READ and LOW to WRITE. Finally, the READY pin 34 may need to be tied to GND.

From a Floppy Maintenance Manual showing the sequence : R/W head > Pre-Amp > Differentiator > Voltage Comparator > Time/Domain Filter > DATA OUT

UPDATES:

I think to make this project work, I would first need to *VERY CAREFULLY* observe the correct functioning of a working device without any changes made to it. I would need to be able to confirm completely the working of the machine, and see what signals are supposed to look like at each step. 

Only after doing this could I start intervening in this process.

I think Floppy is the best way to go – it’s part of the history of the computer (like all my other projects) which isn’t the case with the video recorder. The floppy is the best documented, easiest to source, and least expensive to work with. It already has a nice interface which is easy to use. It also is more standardized, unlike the many different kind of video recorders that exist. 

What is the most standard Floppy Drive Read/Write Amplifier ? The Sony CXA series (1360, 1720, 3010, 3071, 20185, etc.) seem to have specs available online. ROHM also have BH6xxx and BA6xxx series. 

Then again if I’m only going to be recording analog, I don’t need anything but the preamp (especially for reading) ? I could just take the tape preamps I have and put them on a breakout board ? I have BA3110, CX20023, and a CXA1262 to work with. I could try getting them to work amplifying the mic first, and also get the playback working. Then I could test putting analog signals on a floppy.

This workshop with La Diagonale at UP Saclay is a simple circuit to begin playing with code and screen patterns. 

Here is the github: https://github.com/merlinmarrs/spaghettini-video-synth

Arduino Coding and Video Synthesis Workshop

Lean to code in C with Arduino, solder and assemble a custom printed-circuit board made in the Fablab, and make your own algorithmically-generated video art!

This workshop is inspired by the improvisational music of Live coding (https://fr.wikipedia.org/wiki/Live_coding) and the burgeoning minimalist Bytebeats movement (https://nightmachines.tv/bytebeats-tutorial).

Our video synthesis kit plugs in to the Arduino (https://www.arduino.cc/), a reprogrammable embedded micro-controller that can interact with the world through code, and uses the VGAX library (https://github.com/smaffer/vgax) to generate funky video.

Meet other creative technologists and sharpen your expertise in computer sciences and electronics soldering!

Here are some initial sketches :

The functionality that is important is :

-being able to select between different programs (with button and leds to indicate)

-to be able to take audio in and have it modify the patterns on screen

-to be able to change the colors on the go

-I have since phased out the brightness changeability but I could add an LDR easily ?

*******************************************************************************************

Because our lasercutter is not operational, I am trying to make this circuit with the vinyl cutter using 5cm wide copper tape. 

I am worried about the headers getting pulled out when plugging/unplugging. I will try adding some hot glue to fortify them. The other option is potting the circuit in resin but that would get messy and expensive. 

Errata:

-button too close to headers when glue is applied

-remember space for audio in jack plug 

-the two columns of headers for the Arduino should not be continuous, also unclear what is first and last pin. Also they should be SMD headers. 

-don’t mess with RX and TX pins on the Arduino. 

-make a version with VGA plug?

-add text but have it cut onto plastic not made from metal

-audio offset thing doesn’t work

I also want to think about expandability, how could people take this project further by themselves afterwards ?

-Having a knob  or two knobs / LDR connected to an analog in on the Arduino…

-Be able to control the program based on voltage control levels at an input. This could mean it could even be attached to the polyphonic synth !

***************************************************************************

Here is the next version called the Spaghettini:

-It respects the height of the 50mm wide copper tape I have on hand.

-It makes more sense for the audio in cable to plug in at the side and not interfere with the capacitive sensor. 

-It uses curvy lines just for the capacitive sensing functionality and straight elsewhere which feels honest. 

-It has the ability to modify the brightness of any of the three channels, one at a time. 

-It has a potentiometer for analog in in adition the capacitive sensor. 

-I’m experimenting with different patterns on the left portion.

-The sensor works with the Arduino library CapacitiveSensor 

And here’s what it looks like all plugged in ! (But I need to add hot glue to make it really usable)

I have two goals for this project:

1. Finish the VGA video recorder board (with op amps, bias pots, bias for ADC) – DONE!
2. Make a version of the vectorscope image modification series but with a raster system taking the following image as the input – DONE :

1. Finishing the VGA Video Sampler board

For the first goal, I need to correct that last board I made:

Errata:

-The gain pots for the op-amp don’t work.

-I mixed up VCC (3.3V) and VCA (5V) in several places. (I just replaced the PFET with the LDO and manually rewired)

-The “EN” text next to the ADC was in the wrong place. 

-I forgot to tie down the reset of 74HC590 with a 10K resistor.

-The 74HC04 is labelled backwards, I put inputs on the right and outputs on the left for some reason.

Things appear to work with these changes:

It takes some knob fiddling but I can get an input sine wave digitalized. One definitely needs an oscilloscope to see what’s happening though.

2. Vectorscope image series

I can either load the image into memory by playing it on a computer screen and capturing the pixels, OR, loading the image into memory with a microcontroller. I’m not sure how big I should make the image, and what dimensions, if I load the image. 

Here is the p5.js code to take an image (called p.jpg) and print the red pixel value into a text document (called OUTPUT) with a comma and space seperator :

let img;

function preload() {
img = loadImage('p.jpg');
}

function setup() {
createCanvas(img.width, img.height);
background(220);
image(img, 0, 0);
let writer = createWriter('OUTPUT.txt');

for(var y = 0; y < height; y++) {
for(var x = 0; x < width; x++){
let pix = img.get(x, y);
writer.write(pix[0] + ', '); // takes RED pixel info, adds a comma and a space
if(!(y==1-height || x==1-width))
{
writer.write(pix[0]); // don't put a comma if it's the last element of the list
}
}
}
writer.close();
}

And here is the Arduino code to take this color information and load it into the memory space (90×90 max as PROGMEM has max 8,192 bytes max):

byte myChar;

#define IMG_WIDTH 90
#define IMG_HEIGHT 90
//data size=900 bytes
const unsigned char img [IMG_HEIGHT*IMG_WIDTH] PROGMEM={
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0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 118, 255, 251, 43, 0, 29, 239, 255, 115, 1, 0, 1, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 114, 255, 237, 35, 0, 1, 0, 0, 0, 5, 0, 45, 255, 254, 51, 0, 2, 1, 0, 1, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 125, 254, 254, 48, 0, 34, 242, 255, 116, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 2, 1, 3, 2, 0, 0, 1, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 109, 255, 242, 36, 0, 1, 0, 0, 1, 2, 0, 51, 254, 255, 56, 0, 3, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 2, 1, 0, 1, 124, 255, 246, 38, 0, 34, 245, 255, 111, 0, 1, 0, 0, 0, 0, 1, 0, 2, 2, 0, 0, 1, 4, 3, 7, 3, 2, 2, 1, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 108, 255, 218, 7, 0, 0, 0, 1, 0, 3, 0, 44, 254, 255, 50, 0, 0, 0, 0, 0, 0, 1, 1, 1, 2, 0, 0, 1, 3, 3, 1, 1, 3, 1, 1, 0, 1, 1, 4, 2, 2, 0, 0, 0, 0, 0, 0, 0, 128, 255, 243, 36, 0, 40, 246, 255, 157, 9, 23, 32, 30, 17, 29, 13, 0, 1, 0, 24, 61, 25, 0, 1, 0, 0, 1, 0, 0, 34, 32, 0, 1, 0, 1, 12, 6, 0, 2, 19, 22, 0, 128, 255, 240, 36, 0, 2, 1, 1, 0, 1, 1, 64, 255, 255, 64, 1, 10, 7, 10, 10, 16, 6, 0, 0, 0, 10, 35, 13, 1, 0, 0, 0, 0, 0, 0, 6, 8, 0, 0, 0, 0, 3, 8, 6, 7, 8, 2, 0, 150, 255, 248, 43, 0, 27, 229, 255, 255, 247, 242, 246, 243, 233, 254, 216, 46, 0, 43, 217, 255, 242, 61, 0, 23, 11, 18, 0, 94, 255, 255, 102, 2, 6, 121, 253, 228, 215, 220, 241, 250, 176, 197, 255, 255, 204, 6, 1, 0, 0, 2, 1, 8, 214, 255, 238, 243, 222, 230, 223, 225, 226, 255, 150, 0, 0, 49, 217, 255, 189, 22, 18, 37, 36, 41, 22, 75, 228, 250, 83, 0, 1, 44, 203, 245, 227, 226, 226, 224, 223, 249, 255, 251, 46, 0, 23, 231, 255, 254, 255, 255, 254, 255, 255, 255, 254, 255, 255, 255, 255, 255, 255, 255, 254, 255, 255, 255, 255, 252, 255, 255, 255, 255, 255, 255, 254, 255, 255, 255, 255, 254, 255, 255, 255, 255, 241, 33, 0, 1, 0, 1, 0, 14, 224, 255, 255, 255, 255, 255, 255, 255, 255, 254, 255, 255, 255, 255, 255, 255, 255, 254, 255, 255, 255, 255, 255, 255, 255, 254, 255, 253, 254, 255, 255, 255, 255, 255, 254, 255, 255, 255, 255, 244, 39, 0, 10, 122, 153, 147, 144, 138, 142, 134, 131, 131, 138, 145, 136, 124, 122, 125, 139, 148, 151, 158, 139, 129, 143, 40, 74, 144, 135, 128, 127, 106, 109, 116, 106, 102, 99, 110, 117, 114, 97, 129, 96, 0, 0, 0, 0, 0, 0, 0, 102, 138, 112, 123, 116, 117, 107, 114, 131, 132, 140, 135, 135, 130, 112, 137, 86, 86, 118, 105, 101, 100, 108, 94, 93, 101, 103, 119, 120, 105, 100, 103, 102, 101, 99, 97, 95, 89, 83, 63, 7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
// ARRAY OF PIXELS GOES HERE, COMMA + SPACE SEPERATED
};

void setup() {
pinMode (0, OUTPUT);
pinMode (1, OUTPUT);
pinMode (2, OUTPUT);
pinMode (3, OUTPUT);
pinMode (4, OUTPUT);
pinMode (5, OUTPUT);
pinMode (6, OUTPUT);
pinMode (7, OUTPUT); // PORT D

pinMode (8, OUTPUT); // WR PIN (inverted)


for (byte k = 0; k < strlen_P(img); k++) {

digitalWrite(8, LOW); // inverted so this puts WR HIGH (to read)
delay(10);

myChar = pgm_read_byte_near(img + k);
PORTD = myChar;

digitalWrite(8, HIGH); // inverted so this puts WR LOW (to write)
delay(10);

}
}
void loop() {
}